Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

Abstract: A method includes identifying and tracking host threads. A read command is received including a first logical block address (LBA). The first LBA and a first stored LBA in a cache are determined to share a spatial locality. The first LBA and the first stored LBA share a spatial locality when the first LBA is within a predetermined number of LBAs from the first stored LBA. The first stored LBA is removed from the cache responsive to the determination that the first LBA and the first stored LBA share the spatial locality. The first LBA is then added to the cache.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

Abstract: A method includes receiving user data having a number of first bits. The method further includes encoding the user data by generating a number of second encoded bits having a first quantity of bits greater than that of the number of first bits. The number of second encoded bits can include one or more bits having a particular binary value and a quantity of the one or more bits is less than a threshold quantity. The method further includes writing the number of second encoded bits as the user data to a memory.

Abstract: Operations include establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies, communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface, and communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, where a first latency associated with the first data burst command occurs during the second time period.

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, wherein the memory sub-system controller provides a plurality of channel mappings, wherein a first channel mapping of the plurality of channel mappings identifies a first controller channel of the plurality of controller channels and one or more first memory channels of a plurality of memory channels, and wherein a second channel mapping of the plurality of channel mappings identifies a second controller channel of the plurality of controller channels and one or more second memory channels of the plurality of memory channels; one or more memory devices comprising the plurality of memory channels, wherein the one or more memory devices comprise a plurality of memory dies, wherein each memory channel of the plurality of memory channels corresponds to a respective one of the plurality of memory dies; and a channel switch circuit coupled between the plurality of the controller channels and the plurality of m

Abstract: A memory device can include a memory array including memory cells arranged in one or more pages. The memory array can be coupled to control logic to receive a first request to write first data to a page of the one or more pages and program the first data to the page of the one or more pages at a first time responsive to receiving the first request. The control logic is further to receive a second request to write second data to the page of the one or more pages, read the page of the one or more pages, and program the second data to the page of the one or more pages at a second time responsive to receiving the second request. The control logic can also receive an erase request to erase the one or more pages after the second time.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: A memory device of a first array of memory cells configured as quad-level cell (QLC) memory or penta-level cell (PLC) memory and including one or more first planes. A second array of memory cells configured as second memory that is less-densely programmed than the first array, the second array including one or more second planes. Control logic receives a first command to program a first set of memory cells of the first array with a first logical state and a second command to program a second set of memory cells of the second array with a second logical state corresponding in threshold voltage range to the first logical state. The first and second sets of memory cells are associated with a shared wordline. The control logic causes the first and second sets of memory cells to be concurrently programmed with a threshold voltage distribution corresponding to the first logical state.

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

Abstract: Increases in efficiency of storage device operation may be realized if the limited number of available high-priority communication channels are better optimized and assigned among hosts that may best utilize them. This assignment can occur in response to an evaluation of the overall zone usage or by received metadata and/or indicia from the host. The storage device may periodically, or in response to a command, reevaluate the assigned priority status of each communication channel and associated host/zone pair. For example, the storage device may demote or remove a communication channel from high-priority to low-priority. This process can be continued during a preconfigured time window which can be adjusted before, during, or after priority evaluation. The continuous operation of this process can allow for adjustments being made to priority levels within the storage device that may further increase total operational efficiency.

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.

Abstract: Memory with switchable channels is disclosed herein. In one embodiment, a system comprises a controller, a plurality of memory dies, and a switch matrix. The switch matrix is coupled to the controller via two or more controller-side channels, and to the plurality of memory dies via a set of memory-side channels. The switch matrix is configured to selectively couple each controller-side channel of the two or more controller-side channels to each memory-side channel of the set of memory-side channels to provide dynamically configurable connections between the controller and one or more memory dies of the plurality of memory dies.

Abstract: A memory sub-system includes a memory sub-system controller comprising a plurality of controller channels, one or more memory devices, each of which comprises a respective plurality of memory dies, and a channel switch circuit coupled between the plurality of the controller channels and a plurality of memory channels of the one or more memory devices, where each memory channel corresponds to a respective one of the plurality of memory dies of one of the memory devices, the channel switch circuit comprising command processing logic configured to: receive, from the memory sub-system controller, a plurality of channel mappings, each of which identifies a particular one of the controller channels and a particular one of the memory channels, and route data from each controller channel to a respective one of the memory channels that is associated with the controller channel by a respective one of the channel mappings.

Abstract: A memory device includes an interface to communicate with a host, an array of memory cells, and a controller. The controller is configured to access the array of memory cells in response to commands from the host. The controller is further configured to enter an idle time in response to no commands from the host with queue empty, receive a first command from the host, and exit the idle time in response receiving a second command from the host. The controller is further configured to for a plurality of idle times, generate a history indicating a length of each idle time. The controller is further configured to predict the length of a subsequent idle time based on the history.

Abstract: A method includes receiving first data, determining a number of programming operations performed on a plurality of flash memory cells subsequent to a most recent erase operation performed on the plurality of flash memory cells, encoding the first data to provide a first write-once memory (WOM) encoded data, and storing the first WOM encoded data, based at least in part on the determined number of programming operations, within a number of the plurality of flash memory cells.

Abstract: A subset of blocks from a set of blocks of a memory device are identified based on a valid data count constraint. A first block from the subset of blocks is selected based on a valid data count of the first block. A second block from the subset of blocks is selected based on a data temperature of the second block. A comparison of the first block and the second block is performed in accordance with one or more comparison criterion. The first block or the second block is selected as a garbage collection source block based on the comparison. Garbage collection is performed at the garbage collection source block.