Abstract: A power-on control method, a power-on control apparatus and an electronic device are provided in the present disclosure. The power-on control method includes, in response to receiving a power-on command, switching an enable signal of a power control chip from a low level to a high level, and monitoring an output voltage of the power control chip; and performing pulse-width modulation on the enable signal according to an increasing trend of the output voltage to control an increasing rate of the output voltage.

Abstract: A nerve conduit loaded with adipose-derived stem cells and a preparation method thereof are provided. The preparation method includes: S1, adding polycaprolactone and polyvinylpyrrolidone into a binary organic solvent, performing ultrasonic treatment, and then adding reduced graphene oxide nanoparticles to obtain a spinning solution; S2, electrospinning with the spinning solution and then washing for several times to obtain a semi-finished conduit product; and S3, injecting a cell mixture into the semi-finished conduit product to obtain the nerve conduit. A fiber surface of the nerve conduit has groove structures, and thus a specific surface area and cell adhesion sites are increased, and adhesion and proliferation of cells are facilitated.

Abstract: The invention relates to a tailings settling-dewatering-solidifying device and an experimental method thereof, which falls into the technical field of mine engineering and mine geotechnical engineering, comprising a tailings settling device including a water tank, charging barrels I and II, and a reaction tank made of a transparent material, a dewatering device including an intelligent type controller, a circular base, a gas cylinder, a permeable stone, a piston, a metal rod and a water return barrel, a solidifying device including a charging barrel III and a tailings barrel, a stirring system including a stirrer, a rotary shaft and an electric motor, a dynamic real-time monitoring system including a high-definition electronic camera and a computer, and a three-layer framework.

Abstract: The invention relates to a tailings settling-dewatering-solidifying device and an experimental method thereof, which falls into the technical field of mine engineering and mine geotechnical engineering, comprising a tailings settling device including a water tank, charging barrels I and II, and a reaction tank made of a transparent material, a dewatering device including an intelligent type controller, a circular base, a gas cylinder, a permeable stone, a piston, a metal rod and a water return barrel, a solidifying device including a charging barrel III and a tailings barrel, a stirring system including a stirrer, a rotary shaft and an electric motor, a dynamic real-time monitoring system including a high-definition electronic camera and a computer, and a three-layer framework.

Abstract: Apparatuses, systems, and techniques to implement a recurrent neural network. In at least one embodiment, an application programming interface receives one or more API calls comprising a graph definition and a recurrence attribute, and executes a recurrent neural network based on the graph definition.

Abstract: A device compiler and linker is configured to optimize program code of a co-processor enabled application by resolving generic memory access operations within that program code to target specific memory spaces. In situations where a generic memory access operation cannot be resolved and may target constant memory, constant variables associated with those generic memory access operations are transferred to reside in global memory.

Abstract: A device compiler and linker within a parallel processing unit (PPU) is configured to optimize program code of a co-processor enabled application by rematerializing a subset of live-in variables for a particular block in a control flow graph generated for that program code. The device compiler and linker identifies the block of the control flow graph that has the greatest number of live-in variables, then selects a subset of the live-in variables associated with the identified block for which rematerializing confers the greatest estimated profitability. The profitability of rematerializing a given subset of live-in variables is determined based on the number of live-in variables reduced, the cost of rematerialization, and the potential risk of rematerialization.

Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.

Abstract: One embodiment of the present invention sets forth a technique for extracting a memory address offset from a 64-bit type-conversion expression included in high-level source code of a computer program. The technique involves receiving the 64-bit type-conversion expression, where the 64-bit type-conversion expression includes one or more 32-bit expressions, determining a range for each of the one or more 32-bit expressions, calculating a total range by summing the ranges of the 32-bit expressions, determining that the total range is a subset of a range for a 32-bit unsigned integer, calculating the memory address offset based on the ranges for the one or more 32-bit expressions, and generating at least one assembly-level instruction that references the memory address offset.

Abstract: A system and method are provided for inserting synchronization statements into a program file to mitigate race conditions. The method includes reading a program file and determining one or more convergent statements in the program file. The method also includes inserting one or more synchronization statements in the program file between the determined convergent statements. The method further includes removing one or more of the inserted synchronization statements and writing the modified program file. The method may include, after removing the inserted synchronization statements, identifying to a user any remaining inserted synchronization statements.

Abstract: Basic blocks within a thread program are characterized for convergence based on variance analysis or corresponding instructions. Each basic block is marked as divergent based on transitive control dependence on a block that is either divergent or comprising a variant branch condition. Convergent basic blocks that are defined by invariant instructions are advantageously identified as candidates for scalarization by a thread program compiler.

Abstract: Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.

Abstract: A computer program is speculatively parallelized with transactional memory by scoping program variables at compile time, and inserting code into the program at compile time. Determinations of the scoping can be based on whether scalar variables being scoped are involved in inter-loop non-reduction data dependencies, are used outside loops in which they were defined, and at what point in a loop a scalar variable is defined. The inserted code can include instructions for execution at a run time of the program to determine loop boundaries of the program, and issue checkpoint instructions and commit instructions that encompass transaction regions in the program. A transaction region can include an original function of the program and a spin-waiting loop with a non-transactional load, wherein the spin-waiting loop is configured to wait for a previous thread to commit before the current transaction commits.

Abstract: A method for loop reformulation is provided such that a single exit ill-formed loop (SEIFL) can be reformulated into a reformulated code block that contains a transformed well-formed loop (TWFL). A SEIFL loop is a loop that can exit from the loop body of the loop. After the loop reformulation, the TWFL of the reformulated code block can only exit from the end of the loop. The reformulated code block will replace the SEIFL in the compiler's internal representation (IR) such that a more efficient executable machine code can be generated by optimizing the reformulated compiler's IR.

Abstract: Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.

Abstract: A computer program is speculatively parallelized with transactional memory by scoping program variables at compile time, and inserting code into the program at compile time. Determinations of the scoping can be based on whether scalar variables being scoped are involved in inter-loop non-reduction data dependencies, are used outside loops in which they were defined, and at what point in a loop a scalar variable is defined. The inserted code can include instructions for execution at a run time of the program to determine loop boundaries of the program, and issue checkpoint instructions and commit instructions that encompass transaction regions in the program. A transaction region can include an original function of the program and a spin-waiting loop with a non-transactional load, wherein the spin-waiting loop is configured to wait for a previous thread to commit before the current transaction commits.

Abstract: We present a technique to perform dependence analysis on more complex array subscripts than the linear form of the enclosing loop indices. For such complex array subscripts, we decouple the original iteration space and the dependence test iteration space and link them through index-association functions. The dependence analysis is performed in the dependence test iteration space to determine whether the dependence exists in the original iteration space. The dependence distance in the original iteration space is determined by the distance in the dependence test iteration space and the property of index-association functions. For certain non-linear expressions, we show how to transform it to a set of linear expressions equivalently. The latter can be used in dependence test with traditional techniques. We also show how our advanced dependence analysis technique can help parallelize some otherwise hard-to-parallelize loops.

Abstract: Index association based dependence analysis accurately determines lack of dependence for complex memory subscript references to allow greater use of loop transformation and automatic parallelization at compile of an application. Index association functions that map an original i index space to a dependence analysis j index space are analyzed at compile to determine one-to-one mapping or many-to-one mapping. For dependence analysis of two references with a one-to-one mapping determination, lack of dependence in the dependence analysis index space confirms lack of dependence in the original index space. For many-to-one mapping, both a lack of dependence in the dependence analysis index space and a check that no two iterations in the original index space could map to the two references in the dependence analysis index space confirms no dependence for the two references.