Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable Digital Satellite Equipment Control (DiSEqC) communication between an antenna and a processor. An example apparatus includes a receiver to be coupled to an antenna by a cable and configured to bidirectionally communicate with the antenna via a communication signal having a periodic waveform, wherein the receiver further includes a low dropout regulator (LDO) pass transistor to be coupled to the cable and configured to generate a current signal based on the periodic waveform of the communication signal, a current envelope detector circuit coupled to the LDO pass transistor configured to generate a voltage signal based on the current signal, and a processor. The processor is coupled to the current envelope detector circuit and configured to process the voltage signal generated by the current envelope detector.

Abstract: An IC includes an RC filter, a doped layer under a first dielectric layer, a polysilicon layer on the first dielectric layer providing a polysilicon plate for a capacitor of the filter, and gate(s) for MOSFET(s). A second dielectric layer is on the polysilicon plate. An input contact is on one end of the polysilicon plate and an output contact is on the opposite end. A metal layer includes metal providing contact to at least input contact and metal providing contact to the output contact. Analog circuitry includes the MOSFET having an I/O node coupled to the RC filter.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to enable Digital Satellite Equipment Control (DiSEqC) communication between an antenna and a processor. An example apparatus includes a receiver to be coupled to an antenna by a cable and configured to bidirectionally communicate with the antenna via a communication signal having a periodic waveform, wherein the receiver further includes a low dropout regulator (LDO) pass transistor to be coupled to the cable and configured to generate a current signal based on the periodic waveform of the communication signal, a current envelope detector circuit coupled to the LDO pass transistor configured to generate a voltage signal based on the current signal, and a processor. The processor is coupled to the current envelope detector circuit and configured to process the voltage signal generated by the current envelope detector.

Abstract: An IC includes an RC filter, a doped layer under a first dielectric layer, a polysilicon layer on the first dielectric layer providing a polysilicon plate for a capacitor of the filter, and gate(s) for MOSFET(s). A second dielectric layer is on the polysilicon plate. An input contact is on one end of the polysilicon plate and an output contact is on the opposite end. A metal layer includes metal providing contact to at least input contact and metal providing contact to the output contact. Analog circuitry includes the MOSFET having an I/O node coupled to the RC filter.

Abstract: A DC-to-DC converter includes first and second switches. If on, the first switch provides a signal path through a common node to an output voltage node. If on, the second switch provides a signal path through the common node to the output voltage node. Control logic provides first and second control signals to control the first and second switches. A node produces a first voltage that ramps up from zero during initialization, and a soft start controller controls the second control signal while the first voltage is not greater than a predefined level. While the first voltage is not greater than the predefined level, the soft start controller keeps the second control signal at a higher level to maintain on the second switch, and transitions the second control signal to a lower level only when the first control signal transitions from a lower level to a higher level.

Abstract: PWM control circuits and soft start circuitry thereof are presented in which a source follower circuit provides an input to a pulse generator error amplifier during startup according to a lower one of an internal soft start circuit ramp signal and a voltage across and externally connected capacitor, with a current source connected to the source follower to limit the charging current supplied to the externally connected capacitor.

Abstract: A DC-to-DC converter includes first and second switches. If on, the first switch provides a signal path through a common node to an output voltage node. If on, the second switch provides a signal path through the common node to the output voltage node. Control logic provides first and second control signals to control the first and second switches. A node produces a first voltage that ramps up from zero during initialization, and a soft start controller controls the second control signal while the first voltage is not greater than a predefined level. While the first voltage is not greater than the predefined level, the soft start controller keeps the second control signal at a higher level to maintain on the second switch, and transitions the second control signal to a lower level only when the first control signal transitions from a lower level to a higher level.

Abstract: The prevent invention provides an AC-DC flyback converter and a loop compensation method thereof. The AD-DC flyback converter comprises an isolating transformer, a power switch, and a feed control module. The feed control module includes a compensating circuit, a voltage buffer, and an error amplifier having a first resistor and a second resistor, and a pulse width modulation controller. With the AC-DC flyback converter and the loop compensating method, the system stability can be improved and the loop bandwidth can be reduced.

Abstract: PWM control circuits and soft start circuitry thereof are presented in which a source follower circuit provides an input to a pulse generator error amplifier during startup according to a lower one of an internal soft start circuit ramp signal and a voltage across and externally connected capacitor, with a current source connected to the source follower to limit the charging current supplied to the externally connected capacitor.

Abstract: A multiple-input comparator is disclosed. The multiple-input comparator includes a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected to a current source or a current sink. A power inverter utilizing the multiple-input comparator is also disclosed.

Abstract: The prevent invention provides an AC-DC flyback converter and a loop compensation method thereof. The AD-DC flyback converter comprises an isolating transformer, a power switch, and a feed control module. The feed control module includes a compensating circuit, a voltage buffer, and an error amplifier having a first resistor and a second resistor, and a pulse width modulation controller. With the AC-DC flyback converter and the loop compensating method, the system stability can be improved and the loop bandwidth can be reduced.

Abstract: Techniques pertaining to multiple-input comparator and power converter designs are disclosed. According to one aspect, the present invention discloses a multiple-input comparator comprising a pair of differential transistors connected by a resister. The gate terminals of the transistor pair serve as the input terminals of the comparator for receiving external voltage for comparison. The terminal of the resistor serves as the current input terminal and is either connected to a current source or a current sink. A power inverter utilizing the multiple-input comparator is also disclosed. The power inverter comprises a power switch driven by a PMW signal, a voltage sampling circuit, an error amplifier and a multiple-input PWM comparator.

Abstract: Designs of flyback power converters are described. According to one aspect of the designs, a power converter includes a primary side including a primary winding of a transformer coupled to an input voltage and a primary switch for switching on or off the primary winding, a secondary side including a secondary winding of the transformer for generating an output voltage, and a loop controller configured to sample a feedback voltage representative of the output voltage, generate a gate signal with a fixed falling edge and an adjustable rising edge to drive the primary switch, and adjust a duty cycle of the gate signal by adjusting the rising edge of the gate signal until the feedback voltage converges to a reference voltage.