Patents by Inventor Xianjin Wan
Xianjin Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11956953Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: GrantFiled: September 21, 2022Date of Patent: April 9, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Publication number: 20230389323Abstract: A three-dimensional (3D) memory device includes a staircase region including a first stack and a second stack, a barrier structure extending vertically through the first stack and laterally separating the first stack from the second stack, and a through array contact extending vertically through the first stack. The first stack includes first and second dielectric layers arranged alternately in a vertical direction. The second stack includes conductor layers and third dielectric layers arranged alternately in the vertical direction. The barrier structure includes an unclosed shape.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Patent number: 11785776Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: GrantFiled: September 14, 2022Date of Patent: October 10, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Publication number: 20230317665Abstract: In an example, a semiconductor device includes a first semiconductor structure including a memory array device, a second semiconductor structure including a peripheral device, and a bonding structure comprising a first bonding pad, a second bonding pad, and a remainder layer located between and in contact with the first and second bonding pad in a vertical direction. The first bonding pad is located between the remainder layer and the first semiconductor structure in the vertical direction. The second bonding pad is located between the remainder layer and the second semiconductor structure in the vertical direction. A conductive material of the remainder layer is cobalt metal different from the first and second bonding pads.Type: ApplicationFiled: June 6, 2023Publication date: October 5, 2023Inventors: Jie Pan, Shu Liang Lv, Liang Ma, Yuan Li, Si Ping Hu, Xianjin Wan
-
Patent number: 11715718Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.Type: GrantFiled: November 21, 2020Date of Patent: August 1, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jie Pan, Shu Liang Lv, Liang Ma, Yuan Li, Si Ping Hu, Xianjin Wan
-
Publication number: 20230016627Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: ApplicationFiled: September 21, 2022Publication date: January 19, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Publication number: 20230005950Abstract: Embodiments of through array contact structures of a 3D memory device is disclosed. The 3D NAND memory device includes an alternating dielectric stack comprising a plurality of dielectric layer pairs arranged in a vertical direction; n alternating conductor/dielectric stack comprising a plurality of conductor/dielectric layer pairs arranged in the vertical direction; and at least one through array contact extending through the alternating dielectric stack in the vertical direction; a barrier structure separates the alternating dielectric stack and the alternating conductor/dielectric stack, an opening of the barrier structure is at an edge of the alternating dielectric stack along a lateral direction, the lateral direction is perpendicular to the vertical direction.Type: ApplicationFiled: September 14, 2022Publication date: January 5, 2023Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang SHI, Guanping WU, Xianjin WAN, Baoyou CHEN
-
Patent number: 11545505Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: GrantFiled: January 6, 2021Date of Patent: January 3, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Patent number: 11482532Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: GrantFiled: November 18, 2020Date of Patent: October 25, 2022Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Publication number: 20220216178Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.Type: ApplicationFiled: March 24, 2022Publication date: July 7, 2022Inventors: Xinsheng WANG, Li ZHANG, Gaosheng ZHANG, Xianjin WAN, Ziqun HUA, Jiawen WANG, Taotao DING, Hongbin ZHU, Weihua CHENG, Shining YANG
-
Publication number: 20220020725Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a first substrate, and a bonding layer located on a surface of the first substrate. The material of the first bonding layer is a dielectric material containing element carbon (C). C atomic concentration of a surface layer of the first bonding layer away from the first substrate is higher than or equal to 35%. The first bonding layer of the semiconductor structure may be used to enhance bonding strength during bonding.Type: ApplicationFiled: September 29, 2021Publication date: January 20, 2022Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Xinsheng WANG, Li ZHANG, Gaosheng ZHANG, Xianjin WAN, Ziqun HUA, Jiawen WANG, Taotao DING, Hongbin ZHU, Weihua CHENG, Shining YANG
-
Patent number: 11177231Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes a substrate, a first device layer disposed on the substrate, and a first bonding layer disposed above the first device layer and including a first bonding contact. The second semiconductor structure includes a second device layer, and a second bonding layer disposed below the second device layer and including a second bonding contact. The first bonding contact is in contact with the second bonding contact at the bonding interface. At least one of the first bonding contact and the second bonding contact includes a capping layer at the bonding interface and having a conductive material different from a remainder of the respective first or second bonding contact.Type: GrantFiled: September 24, 2018Date of Patent: November 16, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jie Pan, Shu Liang Lv, Liang Ma, Yuan Li, Si Ping Hu, Xianjin Wan
-
Publication number: 20210126005Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: ApplicationFiled: January 6, 2021Publication date: April 29, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Publication number: 20210091033Abstract: Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a method for forming a semiconductor device is disclosed. A first device layer is formed on a first substrate. A first bonding layer including a first bonding contact is formed above the first device layer. A first capping layer is formed at an upper end of the first bonding contact. The first capping layer has a conductive material different from a remainder of the first bonding contact. A second device layer is formed on a second substrate. A second bonding layer including a second bonding contact is formed above the second device layer. The first substrate and the second substrate are bonded in a face-to-face manner, so that the first bonding contact is in contact with the second bonding contact by the first capping layer.Type: ApplicationFiled: November 21, 2020Publication date: March 25, 2021Inventors: Jie Pan, Shu Liang Lv, Liang Ma, Yuan Li, Si Ping Hu, Xianjin Wan
-
Publication number: 20210074718Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: ApplicationFiled: November 18, 2020Publication date: March 11, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu LU, Wenguang SHI, Guanping WU, Feng PAN, Xianjin WAN, Baoyou CHEN
-
Patent number: 10910397Abstract: Embodiments of through array contact structures of a 3D memory device and fabricating method thereof are disclosed. The 3D NAND memory device includes an alternating layer stack disposed on a substrate. The alternating layer stack includes a first region including an alternating dielectric stack, and a second region including an alternating conductor/dielectric stack. The memory device further comprises a barrier structure extending vertically through the alternating layer stack to laterally separate the first region from the second region, and multiple through array contacts in the first region each extending vertically through the alternating dielectric stack. At least one through array contact is electrically connected with a peripheral circuit.Type: GrantFiled: December 26, 2019Date of Patent: February 2, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Xianjin Wan, Baoyou Chen
-
Patent number: 10886291Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: GrantFiled: July 26, 2018Date of Patent: January 5, 2021Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Patent number: 10847532Abstract: Joint opening structures of 3D memory devices and fabricating method are provided. A joint opening structure comprises a first through hole penetrating a first stacked layer and a first insulating connection layer, a first channel structure at the bottom of the first through hole, a first functional layer on the sidewall of the first through hole, a second channel structure on the sidewall of the first functional layer, a third channel structure over the first through hole, a second stacked layer on the third channel structure, a second insulating connection layer on the second stacked layer, a second through hole penetrating the second stacked layer and the second insulating connection layer, a second functional layer disposed on the sidewall of the second through hole, a fourth channel structure on the sidewall of the second functional layer, and a fifth channel structure over the second through hole.Type: GrantFiled: July 26, 2018Date of Patent: November 24, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Zhenyu Lu, Wenguang Shi, Guanping Wu, Feng Pan, Xianjin Wan, Baoyou Chen
-
Patent number: 10818631Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a first substrate; a first adhesive layer disposed on the surface of the first substrate; a first buffer layer disposed on the surface of the first adhesive layer; and a first bonding layer disposed on the surface of the first buffer layer, wherein the densities of the first adhesive layer and the first buffer layer are greater than that of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and the first buffer layer, and the first buffer layer and the first bonding layer exhibit higher adhesion, which are beneficial to improve the performance of the semiconductor structure.Type: GrantFiled: April 7, 2019Date of Patent: October 27, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang
-
Patent number: 10811380Abstract: The present invention relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a first substrate; a first adhesive layer disposed on a surface of the first substrate; and a first bonding layer disposed on a surface of the first adhesive layer. A density of the first adhesive layer is greater than a density of the first bonding layer. The first adhesive layer of the semiconductor structure has higher adhesion with the first substrate and first bonding layer, such that it is advantageous to improve a performance of the semiconductor structure.Type: GrantFiled: April 7, 2019Date of Patent: October 20, 2020Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Xinsheng Wang, Li Zhang, Gaosheng Zhang, Xianjin Wan, Ziqun Hua, Jiawen Wang, Taotao Ding, Hongbin Zhu, Weihua Cheng, Shining Yang