Patents by Inventor Xianjun WU

Xianjun WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240079038
    Abstract: The disclosed driver and memory include: a phase driver that receives a first voltage signal, configured to output a second phase signal according to the first phase signal and the first voltage signal; a complementary phase driver includes: a first inverter for generating a complementary inverted phase signal based on a first complementary phase signal, the first phase signal and the first complementary phase signal are mutually inverted; a second inverter for receiving an output signal of the first inverter and a second voltage signal, the voltage value of the second voltage signal is smaller than that of the first voltage signal, and the second inverter is configured to be based on the first complementary inverted phase signal, and the second voltage signal outputs a second complementary phase signal. The driver of the embodiment provides the second phase signal and the second complementary phase signal.
    Type: Application
    Filed: March 7, 2023
    Publication date: March 7, 2024
    Inventors: Zhonglai Liu, Xianjun Wu, Anping Qiu
  • Patent number: 11848045
    Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.
    Type: Grant
    Filed: August 7, 2021
    Date of Patent: December 19, 2023
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Weibing Shang, Jixing Chen, Xianjun Wu
  • Publication number: 20230280931
    Abstract: Disclosed are a data writing circuit, a data writing method, and a memory. The data writing circuit includes: a delay generation circuit, configured to generate a sub-grab signal of each storage area based on an initial grab signal and data transmission delay of each storage area, and generate a grab enable signal based on all of the sub-grab signals. A time interval between the time that each storage area receives data transmitted by a global data line and the time of receiving a column selection signal meets a preset range. A read-write control circuit writes data on a data bus into the global data line based on the grab enable signal. The global data line transmits the data to the storage area by using a column decoding circuit based on the column selection signal, so as to optimize tCCD of DRAM.
    Type: Application
    Filed: July 1, 2022
    Publication date: September 7, 2023
    Inventors: Xianjun WU, Weibing SHANG
  • Publication number: 20230282268
    Abstract: A circuit includes a delay generation circuit. The delay generation circuit is configured to generate a sub-grab signal for each of the storage areas based on an initial grab signal and data transmission delay of each of the storage areas, and generate a grab enable signal based on all the sub-grab signals. A time interval between a time when the read-write control circuit receives data transmitted from each of the storage areas by a global data line and a time when the read-write control circuit receives the sub-grab signal corresponding to the storage area satisfies a preset range. The read-write control circuit is configured to read out data of the global data line to a data bus based on the grab enable signal. Therefore, the tCCD of the DRAM is optimized.
    Type: Application
    Filed: July 2, 2022
    Publication date: September 7, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xianjun WU, Weibing SHANG
  • Publication number: 20230211245
    Abstract: A remote-control aircraft comprises an aircraft body with a mounting platform provided with a connecting part and first magnet(s), and the connecting part is perforated with a connecting hole; and comprises an aircraft wing with an inserting part and second magnet(s) on its underside close to the aircraft body, the inserting part is rotationally inserted into the connecting hole, the second magnet and the first magnet are connected by magnetic attraction, and the aircraft wing is in close contact with the mounting platform. Thus, the aircraft wing and body can be quickly assembled and disassembled and can be carried conveniently. While the aircraft wing collides with an obstacle, it can be rotated around the inserting part as the center, and the impact force can be unloaded by rotating to prevent the aircraft wing from being damaged and prevent the aircraft wing from being separated from the aircraft body.
    Type: Application
    Filed: April 27, 2022
    Publication date: July 6, 2023
    Applicant: HANGZHOU ZT MODEL CO., LTD.
    Inventors: Rui Feng, Xianjun Wu, He Jiang, Qingsong Qiu
  • Publication number: 20230186970
    Abstract: A decoding drive circuit includes at least one decoding driver. The decoding driver includes a first-stage drive circuit and a second-stage drive circuit. Herein, the first-stage drive circuit is configured to receive an enabling control signal, a decoding input signal and a drive control signal, and generate a first drive signal and a second drive signal according to the enabling control signal, the drive control signal and the decoding input signal. The second-stage drive circuit is configured to generate a target word line drive signal according to the first drive signal and the second drive signal. Thus, the embodiments of the disclosure provide a new decoding drive circuit.
    Type: Application
    Filed: February 8, 2023
    Publication date: June 15, 2023
    Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing SHANG, Xianjun WU, Minghao LI
  • Patent number: 11676642
    Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
    Type: Grant
    Filed: August 18, 2021
    Date of Patent: June 13, 2023
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Weibing Shang, Fengqin Zhang, Kangling Ji, Kai Tian, Xianjun Wu
  • Publication number: 20230170011
    Abstract: Embodiments relate to a decoder driver circuit and a memory chip. The decoder driver circuit includes: a plurality of sub drive units configured to generate a main word line drive signal according to a power supply voltage signal, a first decoding input signal and an intermediate decoding output signal; and a plurality of decoding control circuits connected to the plurality of sub drive units, where the plurality of decoding control circuits are configured to generate the intermediate decoding output signal according to an enable control signal and a second decoding input signal. When the intermediate decoding output signal is in a first state, the main word line drive signal is in a non-drive state.
    Type: Application
    Filed: January 17, 2023
    Publication date: June 1, 2023
    Inventors: Weibing SHANG, Xianjun WU, Minghao LI
  • Publication number: 20220059137
    Abstract: A memory, comprising: a plurality of storage groups, first signal lines and second signal lines. The plurality of storage groups is arranged along a first direction, each one of the storage groups includes multiple banks, which are arranged along a second direction, and the first direction is perpendicular to the second direction; the first signal lines extend along the first direction, each first signal line is arranged correspondingly to more than one of the multiple banks, and configured to transmit storage data of the more than one of the multiple banks; and the second signal lines extend along the first direction, each one of the second signal lines is arranged correspondingly to a respective bank, and configured to transmit the storage data of the respective bank; wherein the first signal lines exchange the storage data with the second signal lines through respective data exchange circuits.
    Type: Application
    Filed: August 18, 2021
    Publication date: February 24, 2022
    Inventors: Weibing SHANG, Fengqin ZHANG, Kangling JI, Kai TIAN, Xianjun WU
  • Publication number: 20210398586
    Abstract: Embodiments of the present invention provide a semiconductor integrated circuit of a memory. The semiconductor integrated circuit can comprise a column selection module, a local read-write conversion module, and an amplifier module. The column selection module can be configured to couple a first data line to a bit line and couple a complementary data line to a complementary bit line. The local read-write conversion module can be configured to perform data transmission from at least one of the first data line or the first complementary data line to a second data line. The data transmission can occur during a memory read-write operation and in response to the local read-write conversion module receiving a read write control signal. The amplifier module can be configured to amplify data of the second data line based on a reference signal of a reference data line. The reference signal can serve as a reference for amplifying the data of the second data line.
    Type: Application
    Filed: August 7, 2021
    Publication date: December 23, 2021
    Inventors: Weibing SHANG, Jixing CHEN, Xianjun WU
  • Patent number: 10710886
    Abstract: The invention provides a method for synthesizing a mesoporous zeolite ETS-10 containing a metal without a templating agent. The method according to the invention comprises the steps of: mixing a silicon source with a NaOH solution to obtain a mixed solution so that the content of Na2O in the mixed solution is 10.0% to 20.0% by weight; adding a KOH or KF solution so that the content of K2O is 10.0% to 25.0% by weight and stirring it well; adding a titanium source solution and stirring it well; adding a precursor compound containing metal Ni and/or Co and stirring it well; and subjecting it to a crystallization reaction to obtain the mesoporous zeolite ETS-10. The mesoporous zeolite ETS-10 obtained by the invention has a specific surface area of 320 to 420 m2/g, a mesoporous volume of 0.11 to 0.21 cm3/g, and thus can be used as a catalyst and a support thereof in synthesis industry for macromolecular fine chemicals.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 14, 2020
    Assignee: PetroChina Company Limited
    Inventors: Tiegang Xu, Tiandi Tang, Wenqian Fu, Lei Zhang, Runsheng Shen, Guoren Cai, Baoli Ma, Weichi Xu, Guangming Wen, Jinhe Song, Dan Wang, Mingwei Tan, Wencheng Zhang, Jintao Guo, Gang Wang, Quanguo Zhang, Xianjun Wu, Liyan Guo, Lei Fang, Liru Cong, Guojia Zhang, Chunming Dong, Yu Liang
  • Patent number: 10683459
    Abstract: Provided are a liquid-phase hydroisomerization system and a process therefor and use thereof. The system comprises a gas-liquid mixer (3), a hydroisomerization reactor (4) and a fractionating column (6). An oil product and hydrogen are mixed as a liquid hydrogen-oil mixture, and are introduced into the hydroisomerization reactor for a hydroisomerization reaction, and after being fractionated, a target product is led out. A supplemental hydrogen-dissolving inner member is provided at least between a group of two adjacent catalyst bed layers in order to supplement hydrogen to the reactants. The process cancels a circulating hydrogen compressor, has a simple process flow, and can be applied to the production of a lubricant base oil by the hydroisomerization of a lubricant raw material or the production of a low freezing point diesel by the hydroisomerization of and the reduction in the freezing point of a diesel raw material.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: June 16, 2020
    Assignee: PetroChina Company Limited
    Inventors: Shoutao Ma, Xiaoqiao Huang, Famin Sun, Qingfeng Ma, Fangming Xie, Yongsheng Duan, Xianjun Wu, Fengxuan Li, Dongmei Ge, Endong Xia, Ruifeng Li, Ronglei Ji, Liying Liu, Lihong Qin, Xiangbin Meng, Chunming Dong, Xuefeng Lu, Rui Wang, Tiegang Xu, Shurong Ni
  • Publication number: 20200071174
    Abstract: The invention provides a method for synthesizing a mesoporous zeolite ETS-10 containing a metal without a templating agent. The method according to the invention comprises the steps of: mixing a silicon source with a NaOH solution to obtain a mixed solution so that the content of Na2O in the mixed solution is 10.0% to 20.0% by weight; adding a KOH or KF solution so that the content of K2O is 10.0% to 25.0% by weight and stirring it well; adding a titanium source solution and stirring it well; adding a precursor compound containing metal Ni and/or Co and stirring it well; and subjecting it to a crystallization reaction to obtain the mesoporous zeolite ETS-10. The mesoporous zeolite ETS-10 obtained by the invention has a specific surface area of 320 to 420 m2/g, a mesoporous volume of 0.11 to 0.21 cm3/g, and thus can be used as a catalyst and a support thereof in synthesis industry for macromolecular fine chemicals.
    Type: Application
    Filed: May 13, 2019
    Publication date: March 5, 2020
    Inventors: Tiegang XU, Tiandi Tang, Wenqian Fu, Lei Zhang, Runsheng Shen, Guoren Cai, Baoli Ma, Weichi Xu, Guangming Wen, Jinhe Song, Dan Wang, Mingwei Tan, Wencheng Zhang, Jintao Guo, Gang Wang, Quanguo Zhang, Xianjun Wu, Liyan Guo, Lei Fang, Liru Cong, Guojia Zhang, Chunming Dong, Yu Liang
  • Patent number: 10258965
    Abstract: The present invention relates to a method for preparing a sulfur-resistant catalyst for aromatics saturated hydrogenation, comprising the steps of: preparing noble metal impregnation solutions from a noble metal and deionized water or an acid solution; impregnating a carrier with the impregnation solutions sequentially from high to low concentrations by incipient impregnation; homogenizing, drying, and calcinating to obtain the sulfur-resistant catalyst for aromatics saturated hydrogenation. The catalyst for aromatics saturated hydrogenation prepared by the method according to the present invention is primarily used in processing low-sulfur and high-aromatics light distillate, middle distillate, atmospheric gas oil, and vacuum gas oil.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: April 16, 2019
    Assignee: PETROCHINA COMPANY LIMITED
    Inventors: Xiaodong Yang, Yanfeng Liu, Sheng Hu, Chunmei Yu, Hongling Chu, Xinmiao Wang, Shanbin Gao, Bin Xie, Famin Sun, Wencheng Zhang, Jintao Guo, Quanguo Zhang, Lili Jiang, Xiaofeng Wang, Yuanyuan Ji, Ran Sun, Yuxiao Feng, Xianjun Wu, Guojia Zhang, Tan Zhao, Wenyong Liu, Rui Li, Ruifeng Li, Cheng Tang
  • Publication number: 20180223194
    Abstract: Provided are a liquid-phase hydroisomerization system and a process therefor and use thereof. The system comprises a gas-liquid mixer (3), a hydroisomerization reactor (4) and a fractionating column (6). An oil product and hydrogen are mixed as a liquid hydrogen-oil mixture, and are introduced into the hydroisomerization reactor for a hydroisomerization reaction, and after being fractionated, a target product is led out. A supplemental hydrogen-dissolving inner member is provided at least between a group of two adjacent catalyst bed layers in order to supplement hydrogen to the reactants. The process cancels a circulating hydrogen compressor, has a simple process flow, and can be applied to the production of a lubricant base oil by the hydroisomerization of a lubricant raw material or the production of a low freezing point diesel by the hydroisomerization of and the reduction in the freezing point of a diesel raw material.
    Type: Application
    Filed: June 8, 2016
    Publication date: August 9, 2018
    Inventors: Shoutao Ma, Xiaoqiao Huang, Famin Sun, Qingfeng Ma, Fangming Xie, Yongsheng Duan, Xianjun Wu, Fengxuan Li, Dongmei Ge, Endong Xia, Ruifeng Li, Ronglei Ji, Liying Liu, Lihong Qin, Xiangbin Meng, Chunming Dong, Xuefeng Lu, Rui Wang, Tiegang Xu, Shurong Ni
  • Publication number: 20160167017
    Abstract: The present invention relates to a method for preparing a sulfur-resistant catalyst for aromatics saturated hydrogenation, comprising the steps of: preparing noble metal impregnation solutions from a noble metal and deionized water or an acid solution; impregnating a carrier with the impregnation solutions sequentially from high to low concentrations by incipient impregnation; homogenizing, drying, and calcinating to obtain the sulfur-resistant catalyst for aromatics saturated hydrogenation. The catalyst for aromatics saturated hydrogenation prepared by the method according to the present invention is primarily used in processing low-sulfur and high-aromatics light distillate, middle distillate, atmospheric gas oil, and vacuum gas oil.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 16, 2016
    Inventors: Xiaodong YANG, Yanfeng LIU, Sheng HU, Chunmei YU, Hongling CHU, Xinmiao Wang, Shanbin GAO, Bin XIE, Famin SUN, Wencheng Zhang, Jintao GUO, Quanguo Zhang, Lili JIANG, Xiaofeng Wang, Yuanyuan JI, Ran SUN, Yuxiao FENG, Xianjun WU, Guojia ZHANG, Tan ZHAO, Wenyong LIU, Rui LI, Ruifeng LI, Cheng TANG