Patents by Inventor Xiankun Jin
Xiankun Jin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961577Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.Type: GrantFiled: July 5, 2022Date of Patent: April 16, 2024Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Xiankun Jin, Mark Lehmann
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Publication number: 20240020186Abstract: A layered architecture for managing health of the electronic system comprises a plurality of health subsystems. Health subsystems receive health information from health monitors coupled to respective components of the electronic system and provide the health information to another health subsystem. Based on the received health information, the other health subsystem uses predictive data analytics to determine a health condition of the electronic system and update a health policy based on the predictive data analytics to improve prediction of the health condition of the electronic system.Type: ApplicationFiled: July 7, 2023Publication date: January 18, 2024Inventors: Xiankun Jin, Andres Barrilado Gonzalez, Mathieu Blazy-Winning
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Publication number: 20240013848Abstract: Analog-to-digital converters (ADCs) of an integrated circuit includes a first set of ADCs and second set of ADCs in which the ADCs of the first set are of a different type than the ADCs of the second set. On-chip testing of the ADCs includes calibrating an N-bit differential digital-to-analog converter (DAC) and storing a pair of calibration codes for each of 2N possible DAC input codes for the DAC in an on-chip memory. The first set of ADCs is tested using the pairs of calibration codes stored in the on-chip memory and a full N-bit resolution of the DAC. Subsequently, the second set of ADCs is tested using pairs of calibration codes corresponding to a reduced M-bit resolution of the DAC, in which M is less than N. During the testing of the second set of ADCs, a portion of the calibration codes stored in the on-chip memory is overwritten.Type: ApplicationFiled: July 5, 2022Publication date: January 11, 2024Inventors: Kumar Abhishek, Xiankun Jin, Mark Lehmann
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Patent number: 11728336Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.Type: GrantFiled: July 29, 2020Date of Patent: August 15, 2023Assignee: NXP USA, Inc.Inventors: Robert S. Jones, III, Xiankun Jin
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Patent number: 11585849Abstract: An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.Type: GrantFiled: July 2, 2019Date of Patent: February 21, 2023Assignee: NXP USA, Inc.Inventors: Tao Chen, Xiankun Jin, Jan-Peter Schat
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Patent number: 11561255Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.Type: GrantFiled: April 15, 2021Date of Patent: January 24, 2023Assignee: NXP USA, Inc.Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
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Publication number: 20220368338Abstract: An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.Type: ApplicationFiled: May 11, 2021Publication date: November 17, 2022Inventors: Xiankun Jin, Douglas Alan Garrity, Mark Lehmann, Kumar Abhishek
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Patent number: 11489535Abstract: Body text indent—does not have paragraph numbering turned on. Not needed in the Abstract. An integrated circuit device includes a digital sine wave generator configured to produce portions of a digital sine wave, a combiner circuit configured to output each of the portions of the digital sine wave combined with a respective calibration code during operation in a post-production dynamic test mode, a digital to analog converter (DAC) configured to output an analog sine wave based on the output of the combiner circuit, and a test analog to digital converter (ADC) including an input terminal directly connected to the output of the DAC, and configured to generate a second digital sine wave based on the analog sine wave.Type: GrantFiled: May 11, 2021Date of Patent: November 1, 2022Assignee: NXP B.V.Inventors: Xiankun Jin, Douglas Alan Garrity, Mark Lehmann, Kumar Abhishek
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Publication number: 20220334176Abstract: An integrated circuit includes an input/output (I/O) circuit configured to receive a first signal and a second signal and a fault detection circuit. The I/O circuit includes an I/O terminal, an I/O buffer, and a pull resistor having a first terminal coupled to the I/O terminal. The fault detection circuit is configured to determine whether a predetermined number of toggles of the first signal occurs while the second signal is held at a constant logic state, assert a fault indicator when the predetermined number of toggles occurs, and negate the fault indicator when the predetermined number of toggles does not occur.Type: ApplicationFiled: April 15, 2021Publication date: October 20, 2022Inventors: Kumar Abhishek, Xiankun Jin, Srikanth Jagannathan
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Patent number: 11418188Abstract: In an integrated circuit, a bootstrapped switch includes a capacitor and first, second, and third transistors. The first transistor has a first current electrode coupled to a first voltage supply node and a gate electrode coupled to a first circuit node. The second transistor has a first current electrode coupled to a second voltage supply terminal, a second current electrode coupled to a top terminal of the capacitor, and a control electrode coupled to the first circuit node. The third transistor has a first current electrode coupled to the first voltage supply terminal, a control electrode coupled to the first circuit node, and a second current electrode coupled to a body terminal of the second transistor. The fourth transistor has a first current electrode coupled to the body terminal of the second transistor, and a second current electrode coupled to the top terminal of the capacitor.Type: GrantFiled: May 11, 2021Date of Patent: August 16, 2022Assignee: NXP B.V.Inventors: Kushagra Bhatheja, Chris C. Dao, Xiankun Jin
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Publication number: 20210003633Abstract: An example apparatus includes a circuit and calibration circuitry. The circuit has complementary input ports to receive input signals including a monotonously rising and/or falling wave reference signal and a voltage-test signal to test at least one direct current (DC) voltage associated with the circuit by comparing the input signals using a first polarity and second polarity associated with the circuit to produce a first output signal and a second output signal. During operation, the circuit manifests an input voltage offset and a signal delay with each comparison of the input signals. The calibration circuitry processes the first and second output signals and, in response, calibrates or sets an adjustment for at least one signal path associated with the circuit in order to account for the input offset voltage and signal delay during normal operation of the circuit.Type: ApplicationFiled: July 2, 2019Publication date: January 7, 2021Inventors: Tao Chen, Xiankun Jin, Jan-Peter Schat
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Patent number: 10866277Abstract: An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.Type: GrantFiled: August 30, 2018Date of Patent: December 15, 2020Assignee: NXP B.V.Inventors: Jan-Peter Schat, Xiankun Jin, Tao Chen
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Publication number: 20200357794Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Robert S. Jones, III, Xiankun Jin
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Patent number: 10816595Abstract: A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.Type: GrantFiled: October 19, 2018Date of Patent: October 27, 2020Assignee: NXP USA, Inc.Inventors: Xiankun Jin, Jan-Peter Schat, Tao Chen, Lei Ma
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Patent number: 10770457Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.Type: GrantFiled: November 6, 2018Date of Patent: September 8, 2020Assignee: NXP USA, Inc.Inventors: Robert S. Jones, III, Xiankun Jin
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Publication number: 20200144253Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Inventors: Robert S. JONES, III, Xiankun JIN
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Publication number: 20200124662Abstract: Embodiments in accordance with the present disclosure are directed to a self-test apparatus for use in an electronic system. The self-test apparatus includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested.Type: ApplicationFiled: October 19, 2018Publication date: April 23, 2020Inventors: Xiankun Jin, Jan-Peter Schat, Tao Chen, Lei Ma
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Publication number: 20200072900Abstract: An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.Type: ApplicationFiled: August 30, 2018Publication date: March 5, 2020Inventors: Jan-Peter Schat, Xiankun Jin, Tao Chen
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Patent number: 10505519Abstract: A dynamic comparator includes two sets of input transistors of opposite conductivity types, where a control electrode of one transistor of each set is coupled to a first input of the comparator and a control input of a second transistor of each set is coupled to a second input of the comparator. The comparator includes bypass transistors for pulling current electrodes of either the first set or second set of input transistors to a power supply terminal depending which input voltage is higher as determined by the output.Type: GrantFiled: June 28, 2019Date of Patent: December 10, 2019Assignee: NXP USA, INC.Inventors: Tao Chen, Xiankun Jin, Jan-Peter Schat
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Patent number: 10474553Abstract: Analog-to-digital conversion is tested in-field using an on-chip built-in self-test (BIST) sub-circuit formed within an underlying integrated circuit. Processing cycles may be conscripted during an idle state when the analog-to-digital conversion is not needed. The BIST requires a test time which may be compared to an idle time. If the idle time exceeds the test time, then the BIST may be entirely performed. However, if the idle time is unknown or less than the test time, the BIST may be paused and resumed between subsequent idle states.Type: GrantFiled: July 18, 2017Date of Patent: November 12, 2019Assignee: NXP USA, Inc.Inventors: Xiankun Jin, Mark Stachew