Abstract: Structures are disclosed for a binned set of two or more pixels of a pixel array that share a same readout circuit. The binned pixel design provides space-saving benefits on the chip and also improves the overall image quality. According to some embodiments, each of the binned pixels includes a photodetector and its own transfer gate. The readout circuit is coupled to the transfer gates of each of the binned pixels and includes its own second transfer gate that separates the pixels from a gain mode select block. The gain mode select block may include capacitors of different sizes and one or more switches to control which capacitors are to receive the charge from any one of the binned pixels. The readout circuit may also include a potential barrier (such as a diode), which allows for pumping charge onto the one or more capacitors of the gain mode select block.

Abstract: A given pixel of a pixel array includes various operation modes with each of the operation modes having a different conversion gain for the charge received from the photodetector of the pixel. When the modes are used in conjunction with one another, the dynamic range of the pixel can be increased. A readout circuit coupled to a photodetector within a given pixel includes a transfer gate between the photodetector and a gain mode select block that includes capacitors of different sizes and one or more switches to control which capacitors are to receive the charge from the photodetector. Depending on the state(s) of the one or more switches, different operation modes with different conversion gains can be selected to increase the dynamic range of the pixel. The adaptability of the readout circuit can allow for a high dynamic range even in extreme temperature environments by lowering the dark current.

Abstract: A given pixel of a pixel array includes various operation modes with each of the operation modes having a different conversion gain for the charge received from the photodetector of the pixel. When the modes are used in conjunction with one another, the dynamic range of the pixel can be increased. A readout circuit coupled to a photodetector within a given pixel includes a transfer gate between the photodetector and a gain mode select block that includes capacitors of different sizes and one or more switches to control which capacitors are to receive the charge from the photodetector. Depending on the state(s) of the one or more switches, different operation modes with different conversion gains can be selected to increase the dynamic range of the pixel. The adaptability of the readout circuit can allow for a high dynamic range even in extreme temperature environments by lowering the dark current.

Abstract: A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit.

Abstract: A sensor includes a photodiode disposed in a semiconductor material to receive light and convert the light into charge, and a first floating diffusion coupled to the photodiode to receive the charge. A second floating diffusion is coupled to the photodiode to receive the charge, and a first transfer transistor is coupled to transfer the charge from the photodiode into the first floating diffusion. A second transfer transistor is coupled to transfer the charge from the photodiode into the second floating diffusion, and an inductor is coupled between a first gate terminal of the first transfer transistor and a second gate terminal of the second transfer transistor. The inductor, the first gate terminal, and the second gate terminal form a resonant circuit.

Abstract: A front-side-interconnect (FSI) red-green-blue-infrared (RGB-IR) photosensor array has photosensors of a first type with a diffused N-type region in a P-type well, the P-type well diffused into a high resistivity semiconductor layer; photosensors of a second type, with a deeper diffused N-type region in a P-type well, the P-type well; and photosensors of a third type with a diffused N-type region diffused into the high resistivity semiconductor layer underlying all of the other types of photosensors. In embodiments, photosensors of a fourth type have a diffused N-type region in a P-type well, the N-type region deeper than the N-type region of photosensors of the first and second types.

Abstract: An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor material between the photodiode and the storage diode. Further, the buried storage well may be disposed under the storage diode and partially under the transfer storage gate. Additionally, a length of the transfer storage gate and a length of the storage diode may be equal, and the storage diode may passivate a surface of the semiconductor material between the transfer storage gate and an output gate.

Abstract: An image sensor pixel having a hybrid transfer storage gate-storage diode storage node is disclosed herein. An example image sensor includes a photodiode, a storage diode, a transfer gate, and a buried storage well. The photodiode, storage diode, and buried storage well are all disposed in a semiconductor material. The transfer storage gate may be disposed on a surface of the semiconductor material between the photodiode and the storage diode. Further, the buried storage well may be disposed under the storage diode and partially under the transfer storage gate. Additionally, a length of the transfer storage gate and a length of the storage diode may be equal, and the storage diode may passivate a surface of the semiconductor material between the transfer storage gate and an output gate.

Abstract: A front-side-interconnect (FSI) red-green-blue-infrared (RGB-IR) photosensor array has photosensors of a first type with a diffused N-type region in a P-type well, the P-type well diffused into a high resistivity semiconductor layer; photosensors of a second type, with a deeper diffused N-type region in a P-type well, the P-type well; and photosensors of a third type with a diffused N-type region diffused into the high resistivity semiconductor layer underlying all of the other types of photosensors. In embodiments, photosensors of a fourth type have a diffused N-type region in a P-type well, the N-type region deeper than the N-type region of photosensors of the first and second types.

Abstract: A storage transistor with a storage region is disposed in a semiconductor material. A gate electrode is disposed in a bottom side of an interlayer proximate to the storage region, and a dielectric layer is disposed between the storage region and the gate electrode. An optical isolation structure is disposed in the interlayer and the optical isolation structure extends from a top side of the interlayer to the gate electrode. The optical isolation structure is also adjoining a perimeter of the gate electrode and contacts the gate electrode. A capping layer is disposed proximate to the top side of the interlayer and the capping layer caps a volume encircled by the optical isolation structure.

Abstract: An image sensor pixel includes a photodiode, a first storage node, a second storage node, a first transfer storage gate, a second transfer storage gate, a floating diffusion, and an output gate. The photodiode is for generating image charge in response to image light. The first storage node, the second storage node, and the photodiode have a first doping polarity. The first transfer storage gate is coupled to transfer the image charge from the photodiode to the first storage node. The first transfer storage gate is disposed over a majority portion of the first storage node. The second transfer storage gate is coupled to transfer the image charge from the first storage node to the second storage node. The second transfer storage gate is disposed over a majority portion of the second storage node. The output gate transfers the image charge from the second storage node to the floating diffusion.

Abstract: A storage transistor with a storage region is disposed in a semiconductor material. A gate electrode is disposed in a bottom side of an interlayer proximate to the storage region, and a dielectric layer is disposed between the storage region and the gate electrode. An optical isolation structure is disposed in the interlayer and the optical isolation structure extends from a top side of the interlayer to the gate electrode. The optical isolation structure is also adjoining a perimeter of the gate electrode and contacts the gate electrode. A capping layer is disposed proximate to the top side of the interlayer and the capping layer caps a volume encircled by the optical isolation structure.

Abstract: An image sensor pixel includes a photodiode, a first storage node, a second storage node, a first transfer storage gate, a second transfer storage gate, a floating diffusion, and an output gate. The photodiode is for generating image charge in response to image light. The first storage node, the second storage node, and the photodiode have a first doping polarity. The first transfer storage gate is coupled to transfer the image charge from the photodiode to the first storage node. The first transfer storage gate is disposed over a majority portion of the first storage node. The second transfer storage gate is coupled to transfer the image charge from the first storage node to the second storage node. The second transfer storage gate is disposed over a majority portion of the second storage node. The output gate transfers the image charge from the second storage node to the floating diffusion.

Abstract: An image sensor with an array of image sensor pixels is provided. Each pixel may include a photodiode and associated pixel circuits formed in a semiconductor substrate. Buried light shields may be formed on the substrate to present pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. Metal interconnect muting structures may be formed over the buried light shields. In one embodiment, light blocking structures may be formed to completely seal the interconnect routing structures. The light blocking structures may be formed on top of the buried light shields or on the surface of the substrate. In another embodiment, planar light blocking structures that are parallel to the surface of the substrate may be formed between metal routing layers to help absorb stray light. Light blocking structures formed in these ways can help reduce optical crosstalk and enhance global shutter efficiency.

Abstract: An image sensor includes a plurality of photodiodes arranged into an array of rows and columns. The photodiodes are grouped into pixel units, where each pixel unit includes at least four photodiodes and shared pixel unit circuitry coupled to each of the four photodiodes. In one aspect the shared pixel unit circuitry may include a shared source follower transistor. In another aspect the shared pixel unit circuitry includes a shared reset transistor. Two of the photodiodes of the pixel unit are in a first column of the array and another two of the photodiodes are in a second column of the array. One of the photodiodes in the second column is in a row that is between rows of the two photodiodes in the first column.

Abstract: A photodiodes may be formed on a substrate such as an imager substrate. The photodiode may include first and second layers in the substrate that form a p-n junction. The first layer may have a first doping type such as p-type doping, whereas the second layer may have a second, opposite doping type such as n-type doping. A counter-doping implant region may be provided that only partially overlaps with the second layer of the photodiode. The counter-doping implant region may have an opposite doping type to the second layer and may have a dopant concentration that is less than the dopant concentration of the second layer. The counter-doping implant region may extend into a third layer of the substrate that may have the same doping type of the second layer but at a lower concentration than the counter-doping implant region.

Abstract: An image sensor with an array of image sensor pixels is provided. Each pixel may include a photodiode and associated pixel circuits formed in a semiconductor substrate. Buried light shields may be formed on the substrate to present pixel circuitry that is formed in the substrate between two adjacent photodiodes from being exposed to incoming light. Metal interconnect muting structures may be formed over the buried light shields. In one embodiment, light blocking structures may be formed to completely seal the interconnect routing structures. The light blocking structures may be formed on top of the buried light shields or on the surface of the substrate. In another embodiment, planar light blocking structures that are parallel to the surface of the substrate may be formed between metal routing layers to help absorb stray light. Light blocking structures formed in these ways can help reduce optical crosstalk and enhance global shutter efficiency.

Abstract: A backside illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a front surface of a semiconductor substrate. Silicon inner microlenses may be formed on a back surface of the semiconductor substrate. In particular, positive inner microlenses may be formed over the photodiodes, whereas negative inner microlenses may be formed over the associated pixel circuits. Buried light shielding structures may be formed over the negative inner microlenses to prevent pixel circuitry that is formed in the substrate between two neighboring photodiodes from being exposed to incoming light. The buried light shielding structures may be lined with absorptive antireflective coating material to prevent light from being reflected off the surface of the buried light shielding structures.

Abstract: A backside illuminated image sensor with an array of image sensor pixels is provided. Each image pixel may include a photodiode and associated pixel circuits formed in a front surface of a semiconductor substrate. Silicon inner microlenses may be formed on a back surface of the semiconductor substrate. In particular, positive inner microlenses may be formed over the photodiodes, whereas negative inner microlenses may be formed over the associated pixel circuits. Buried light shielding structures may be formed over the negative inner microlenses to prevent pixel circuitry that is formed in the substrate between two neighboring photodiodes from being exposed to incoming light. The buried light shielding structures may be lined with absorptive antireflective coating material to prevent light from being reflected off the surface of the buried light shielding structures.

Abstract: A photodiodes may be formed on a substrate such as an imager substrate. The photodiode may include first and second layers in the substrate that form a p-n junction. The first layer may have a first doping type such as p-type doping, whereas the second layer may have a second, opposite doping type such as n-type doping. A counter-doping implant region may be provided that only partially overlaps with the second layer of the photodiode. The counter-doping implant region may have an opposite doping type to the second layer and may have a dopant concentration that is less than the dopant concentration of the second layer. The counter-doping implant region may extend into a third layer of the substrate that may have the same doping type of the second layer but at a lower concentration than the counter-doping implant region.