Abstract: An annular time-to-digital converter includes a pulse shaper that shapes an input start pulse and an input stop pulse to form fixed-width pulses for output. The annular time-to-digital converter also includes at least two differential comparing units that enable, during matching enabling, triggers of the differential comparing units to set setting ends to 1. A circle counter counts the number of times a pulse is propagated in a loop. A matching enabling logical device generates a matching enabling signal, and sends the generated matching enabling signal to comparing enabling ports of the differential comparing units. At least two in-loop position encoders find a position of a first matched unit according to matching signals sent by the differential comparing units. Result recording registers record the number of circles and in-loop positions when matching occurs. High resolution is realized using a differential chain, and wafer area is saved by the annular design.

Abstract: An annular time-to-digital converter includes a pulse shaper that shapes an input start pulse and an input stop pulse to form fixed-width pulses for output. The annular time-to-digital converter also includes at least two differential comparing units that enable, during matching enabling, triggers of the differential comparing units to set setting ends to 1. A circle counter counts the number of times a pulse is propagated in a loop. A matching enabling logical device generates a matching enabling signal, and sends the generated matching enabling signal to comparing enabling ports of the differential comparing units. At least two in-loop position encoders find a position of a first matched unit according to matching signals sent by the differential comparing units. Result recording registers record the number of circles and in-loop positions when matching occurs. High resolution is realized using a differential chain, and wafer area is saved by the annular design.