Abstract: A prefetcher, an operating method of the prefetcher, and a processor including the prefetcher are provided. The prefetcher includes a prefetch address generating circuit, an address tracking circuit, and an offset control circuit. The prefetch address generating circuit generates a prefetch address based on first prefetch information and an offset amount. The address tracking circuit stores the prefetch address and a plurality of historical prefetch addresses. When receiving an access address, the offset control circuit updates the offset amount based on second prefetch information, the access address, the prefetch address, and the historical prefetch addresses, and provides the prefetch address generating circuit with the updated offset amount.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Abstract: The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Abstract: A prefetcher, an operating method of the prefetcher, and a processor including the prefetcher are provided. The prefetcher includes a prefetch address generating circuit, an address tracking circuit, and an offset control circuit. The prefetch address generating circuit generates a prefetch address based on first prefetch information and an offset amount. The address tracking circuit stores the prefetch address and a plurality of historical prefetch addresses. When receiving an access address, the offset control circuit updates the offset amount based on second prefetch information, the access address, the prefetch address, and the historical prefetch addresses, and provides the prefetch address generating circuit with the updated offset amount.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: An optimized communication technique is provided. A communication controller has a retransmission list and a destination control logic circuit. The retransmission list records an identification number of a communication transaction that failed to transmit from a source module to a destination module. The destination control logic circuit manages the retransmission list. When a tracker is released from a queue of the destination module, the destination control logic circuit requests the source module to retransmit the communication transaction to the destination module according to the identification number recorded in the retransmission list.

Abstract: An optimized communication technique is provided. A transaction capability table records a first value representing practical transaction capability of a source module for transmitting a communication transaction to a destination module. Exchange of transaction capability regarding the destination module between the source module and at least one neighboring source module is taken into account in the first value. The source control logic circuit manages the transaction capability table and controls the source module to transmit a communication transaction to the destination module based on the first value recorded in the transaction capability table.