Patents by Inventor Xianri Huang

Xianri Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for correcting error in a PLL generated clock signal using a system clock of lower frequency and/or accuracy
    Patent number: 8677172
    Abstract: The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: March 18, 2014
    Assignee: ST-Ericsson SA
    Inventors: Peter Anderson, Jacqueline Bickerstaff, Xianri Huang
  • Method and System for Detecting Timing Characteristics in a Communications System
    Publication number: 20110068828
    Abstract: The present invention provides a system for detecting timing characteristics of internal signals in a communications device, the system comprising: a system clock running at a known frequency; a test counter having a test input at which an internal signal to be tested is received; a gating counter having an input arranged to receive the system clock signal; and a system controller for controlling the counters; wherein the system controller controls the gating counter to count a predetermined number of system clock cycles to define a test period, and during the test period the test counter counts the cycles of the internal signal under test, whereby timing characteristics of the internal signal may be found with reference to a time base defined by the system clock. An associated method of operation is also described.
    Type: Application
    Filed: April 21, 2009
    Publication date: March 24, 2011
    Inventors: Peter Anderson, Jacqueline Bickerstaff, Xianri Huang