Patents by Inventor Xianwei Ying

Xianwei Ying has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11011472
    Abstract: The present invention discloses a self-aligned register structure for base polysilicon and a preparation method thereof. The self-aligned register structure comprises a silicon substrate having a partially oxidized region of SiO2 medium, a SiO2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO2 medium protective layer, the adjacent base polysilicon layers are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 18, 2021
    Assignee: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 55 RESEARCH INSTITUTE
    Inventors: Hongjun Liu, Xianwei Ying, Yangyang Zhao, Guoxing Sheng
  • Publication number: 20200066649
    Abstract: The present invention discloses a self-aligned register structure for base polysilicon and a preparation method thereof. The self-aligned register structure comprises a silicon substrate having a partially oxidized region of SiO2 medium, a SiO2 medium protective layer is arranged at a center above the silicon substrate, base polysilicon layers are located at left and right sides of the SiO2 medium protective layer, the adjacent base polysilicon layers are symmetrical to the SiO2 medium protective layer at equal spacing, and the spacing is equal to a thickness of the base polysilicon layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: February 27, 2020
    Applicant: CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION NO. 55 RESEARCH INSTITUTE
    Inventors: Hongjun LIU, Xianwei YING, Yangyang ZHAO, Guoxing SHENG
  • Publication number: 20130137235
    Abstract: A MOS transistor (60, 62) is provided. The structure of the transistor (60, 62) includes: a semiconductor substrate (10), a channel area (20, 24), source/drain regions (22, 26), a gate (30, 32), a gate insulating layer (11), a shallow trench isolation region (12), a passive layer (50, 52), and holes (40, 42) formed with a certain distance to the gate insulating layer (11). Wherein both the shapes of the holes (40, 42) and the Young's modulus' difference between the material in the holes (40, 42) and that around the holes (40, 42) contribute to the stress concentration effect, thus the stress in the channel area (20, 24) is enhanced. The structure of the transistor (60, 62) can greatly reduce the stress attenuation during the transmission from stress resource to the sensitive region, and concentrate the stress in the sensitive region. The structure can be involved in large size device, especially.
    Type: Application
    Filed: April 22, 2011
    Publication date: May 30, 2013
    Applicant: University of Electronic Science and Technology of China
    Inventors: Qi Yu, Xiangzhan Wang, Ning Ning, Jingchun Li, Hongdong Yang, Xianwei Ying, Weijie Zhou, Bin Jiang, Yong Wang