Publication number: 20130137235
Abstract: A MOS transistor (60, 62) is provided. The structure of the transistor (60, 62) includes: a semiconductor substrate (10), a channel area (20, 24), source/drain regions (22, 26), a gate (30, 32), a gate insulating layer (11), a shallow trench isolation region (12), a passive layer (50, 52), and holes (40, 42) formed with a certain distance to the gate insulating layer (11). Wherein both the shapes of the holes (40, 42) and the Young's modulus' difference between the material in the holes (40, 42) and that around the holes (40, 42) contribute to the stress concentration effect, thus the stress in the channel area (20, 24) is enhanced. The structure of the transistor (60, 62) can greatly reduce the stress attenuation during the transmission from stress resource to the sensitive region, and concentrate the stress in the sensitive region. The structure can be involved in large size device, especially.
Type:
Application
Filed:
April 22, 2011
Publication date:
May 30, 2013
Applicant:
University of Electronic Science and Technology of China
Inventors:
Qi Yu, Xiangzhan Wang, Ning Ning, Jingchun Li, Hongdong Yang, Xianwei Ying, Weijie Zhou, Bin Jiang, Yong Wang