Patents by Inventor Xianwu LUO

Xianwu LUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12277072
    Abstract: Aspects of the disclosure provide the memory system having a memory apparatus and a memory controller coupled with the memory apparatus. The memory apparatus includes at least one memory chip having a plurality of memory planes, each memory plane includes a plurality of pages, a plurality of pages located at the same position in each of the memory planes of the at least one memory chip form a page line, the memory apparatus includes a plurality of tag groups, each tag group includes a plurality of page lines. The memory controller can be configured to, when the memory apparatus is powered down and then powered on, respectively perform, in sequence, a recoding operation on all pages of which the states are programmed states in each tag group, and according to an encoding result corresponding to each tag group, respectively determine whether check data corresponding to each tag group is abnormal.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: April 15, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventor: Xianwu Luo
  • Patent number: 12236100
    Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.
    Type: Grant
    Filed: December 29, 2022
    Date of Patent: February 25, 2025
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jin Cai, Xianwu Luo
  • Publication number: 20240378115
    Abstract: In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)th word line and ith RAID parity data to obtain (i+1)th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, the (i+1)th RAID parity data overwriting the ith RAID parity data, i being a positive integer greater than or equal to 1.
    Type: Application
    Filed: July 23, 2024
    Publication date: November 14, 2024
    Inventors: Xianwu Luo, Jiangwei Shi, Youxin He
  • Patent number: 12079085
    Abstract: In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)th word line and ith RAID parity data to obtain (i+1)th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, the (i+1)th RAID parity data overwriting the ith RAID parity data, i being a positive integer greater than or equal to 1.
    Type: Grant
    Filed: December 30, 2022
    Date of Patent: September 3, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xianwu Luo, Jiangwei Shi, Youxin He
  • Publication number: 20240220169
    Abstract: A memory system includes a memory device configured to store memory data. The memory device includes an array of memory cells, and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The memory system also includes a memory controller coupled to the array of memory cells. The memory controller is configured to receive the memory data and first parity data of the memory data, perform a redundant array of independent disks (RAID) encode operation on the memory data and the first parity data to form second parity data, and perform a write operation to store the memory data, the first parity data, and the second parity data into the array of memory cells.
    Type: Application
    Filed: March 13, 2024
    Publication date: July 4, 2024
    Inventor: Xianwu LUO
  • Publication number: 20240211144
    Abstract: The present disclosure is directed to an operating method of a memory controller, a memory controller, a memory system, and an electronic device. Herein, the operating method can include determining a backup region to be used in an idle state from a memory array, when detecting that remaining capacity of a currently used backup region for storing redundancy parity data in the memory array is less than a required capacity of redundancy parity data to be written, determining the quantity of all backup regions for storing redundancy parity data including the backup region to be used in the memory array, deciding whether the quantity is larger than a preset threshold, and erasing backup regions having stored redundancy parity data in the memory array when the quantity is larger than the preset threshold.
    Type: Application
    Filed: December 29, 2022
    Publication date: June 27, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jin CAI, Xianwu LUO
  • Publication number: 20240176499
    Abstract: Disclosed in the present application are an operating method for a memory controller, a memory controller, a system, and an electronic device. The operating method can include, when detecting that remaining capacity of a used backup area in the memory is less than capacity required for redundancy check data to be written, determining a backup area to be used from the memory, determining valid redundancy check data belonging to garbage collection in the used backup area, and backing up the valid redundancy check data into the backup area to be used, and erasing the used backup area.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 30, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: Xianwu LUO, Jin CAI
  • Publication number: 20240176519
    Abstract: The present application discloses example operating methods for memory controllers, memory controllers, systems, and electronic devices. The operating methods include: in response to a working mode switching command, determining a state of redundancy check data in a redundancy check cache of a memory controller, and the redundancy check data being used for data recovery of a corresponding storage area in a memory array; and backing up the redundancy check data in the state of an updated state into a backup area of the memory array. Other examples are described.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 30, 2024
    Inventors: Jin Cai, Xianwu Luo
  • Publication number: 20240168849
    Abstract: In once example, a memory system includes a controller and a three-dimensional non-volatile memory that are coupled. The three-dimensional non-volatile memory includes a three-dimensional memory array. The three-dimensional memory array includes a plurality of word lines and a plurality of pages that are coupled. The controller is configured to: calculate received page data corresponding to a first word line in units of page data corresponding to one word line to obtain first RAID parity data, and store the first RAID parity data in a parity buffer space; and calculate received page data corresponding to an (i+1)th word line and ith RAID parity data to obtain (i+1)th RAID parity data, and store the (i+1)th RAID parity data in the parity buffer space, the (i+1)th RAID parity data overwriting the ith RAID parity data, i being a positive integer greater than or equal to 1.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 23, 2024
    Inventors: Xianwu Luo, Jiangwei Shi, Youxin He
  • Publication number: 20240168892
    Abstract: Aspects of the disclosure provide the memory system having a memory apparatus and a memory controller coupled with the memory apparatus. The memory apparatus includes at least one memory chip having a plurality of memory planes, each memory plane includes a plurality of pages, a plurality of pages located at the same position in each of the memory planes of the at least one memory chip form a page line, the memory apparatus includes a plurality of tag groups, each tag group includes a plurality of page lines. The memory controller can be configured to, when the memory apparatus is powered down and then powered on, respectively perform, in sequence, a recoding operation on all pages of which the states are programmed states in each tag group, and according to an encoding result corresponding to each tag group, respectively determine whether check data corresponding to each tag group is abnormal.
    Type: Application
    Filed: December 29, 2022
    Publication date: May 23, 2024
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventor: Xianwu LUO
  • Patent number: 11972155
    Abstract: Implementations of the present disclosure provide a system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includes a memory controller, having a processor and a memory, operatively coupled to the array of memory cells. The system further includes a host, having another processor and another memory, operatively coupled to the memory controller. The other processor of the host is configured to perform a first RAID encode operation on memory data to form first parity data. The processor of the memory controller is configured to receive the first parity data and the memory data, and perform a second RAID encode operation on the first parity data and the memory data to form second parity data.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: April 30, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: Xianwu Luo
  • Publication number: 20230072348
    Abstract: Implementations of the present disclosure provide a system includes a memory device for storing memory data. The memory device includes an array of memory cells and a plurality of word lines arranged in a plurality of rows and coupled to the array of memory cells. The system also includes a memory controller, having a processor and a memory, operatively coupled to the array of memory cells. The system further includes a host, having another processor and another memory, operatively coupled to the memory controller. The other processor of the host is configured to perform a first RAID encode operation on memory data to form first parity data. The processor of the memory controller is configured to receive the first parity data and the memory data, and perform a second RAID encode operation on the first parity data and the memory data to form second parity data.
    Type: Application
    Filed: September 29, 2021
    Publication date: March 9, 2023
    Inventor: Xianwu LUO