Abstract: A method and a device for preparing a carbon nanotube and a prepared carbon nanotube. The method includes: adding iron pentcarbonyl and nickel tetracarbonyl into a multi-stage series fluidized bed and performing decomposition to obtain a catalyst, and discharging the carbon monoxide generated; adding a carbon source and injecting an inert gas into the series fluidized bed for reaction under heating at 600-800° C. for 40-90 min, the ratio of the mass of carbon in the carbon source to the mass of the catalyst being 5-7:3-5. Further provided are a device for preparing a carbon nanotube according to the above method and a carbon nanotube prepared by the above method.

Abstract: A method and a device for preparing a carbon nanotube and a prepared carbon nanotube. The method includes: adding iron pentcarbonyl and nickel tetracarbonyl into a multi-stage series fluidized bed and performing decomposition to obtain a catalyst, and discharging the carbon monoxide generated; adding a carbon source and injecting an inert gas into the series fluidized bed for reaction under heating at 600-800° C. for 40-90 min, the ratio of the mass of carbon in the carbon source to the mass of the catalyst being 5-7:3-5. Further provided are a device for preparing a carbon nanotube according to the above method and a carbon nanotube prepared by the above method.

Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.

Abstract: Apparatus and method generally relating to load detection associated with an analog video port are disclosed. An embodiment of the apparatus for detection of a remote termination resistance includes a pulse detection circuit configured to generate a detection pulse within a blanking interval. A pulse insertion circuit is coupled to receive the detection pulse and is configured to insert the detection pulse onto a line, where the line is an analog color signal line.

Abstract: Multi-mode charger device for charging portable devices and methods of charging portable devices are described. In an embodiment, a multi-mode charger device has mode blocks respectively associated with modes of operation which are coupled to a switch module. The switch module is for coupling a selected one of the mode blocks to a peripheral bus and to decouple the mode blocks remaining from the peripheral bus. A first mode of the modes of operation is a pass through mode. A second mode of the modes of operation is a first charging mode. A third mode of the modes of operation is a second charging mode. The first charging mode and the second charging mode are different from one another.

Abstract: A bus switch chip is limited to operating with a power-supply voltage of 1.8 volts relative to a 0-volt ground. Differential bus signals switched through the bus switch chip swing from 2.7 to 3.3 volts, well above the chip's specified power-supply voltage. The bus switch chip is level-shifted by applying a 1.5-volt signal as the chip's ground, and a 3.3-volt signal as its power supply, so the chip's net power supply is within the specification at 1.8 volts. High-Definition Multimedia Interface (HDMI) and Digital Visual Interface (DVI) require that the differential signals are never driven to ground. However, some non-compliant video transmitters drive differential signals to ground when disabled. External pullup resistors or internal pullup transistors in the bus switch chip are added to the bus signals from non-compliant transmitters to pull disabled signals above the 1.5-volt chip ground to prevent damage from signals below the chip's 1.5-volt ground.

Abstract: A bi-directional bus-interface chip has no direction-control input. A forward buffer and a reverse buffer are both normally disabled in the high-impedance state. When a transition occurs on one input bus, a driver transistor in the forward or reverse buffer is activated to pass the transition through the bus-interface chip. After a delay, the driver transistor is disabled. An optional bus-hold circuit maintains voltage levels on buses when driver transistors are disabled. The delay can be selectable by shorting delay resistors in the delay circuit. The high-level voltages on the two busses may differ. The bus-interface chip converts one voltage domain to another and can re-generate weak signals. A pre-buffer may be added to gradually step up the voltage level when differences in voltage domains are large.

Abstract: Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass capacitor. The time delay of the on stage of the MOSFET inhibits ground current generated by EOS voltage leaked from the power supply through parasitic resistances, capacitances, and inductances, preventing ESD-protection diodes inside the chip from burning out from this EOS pulses that occur during hot insertion. The ESD bypass capacitor shunts the initial ESD pulse to ground before the external MOSFET turns on.

Abstract: Electro-static-discharge (ESD) protection of an integrated circuit chip is enhanced by an EOS protection circuit using external components. An external MOSFET is placed in series with the ground pin of the integrated circuit chip. The external MOSFET has a gate coupled to a power bus through a gate resistor, and is bypassed by an ESD capacitor. The external MOSFET turns on after a delay when power is applied during hot insertion. The delay is determined by a power-to-ground bypass capacitor. The time delay of the on stage of the MOSFET inhibits ground current generated by EOS voltage leaked from the power supply through parasitic resistances, capacitances, and inductances, preventing ESD-protection diodes inside the chip from burning out from this EOS pulses that occur during hot insertion. The ESD bypass capacitor shunts the initial ESD pulse to ground before the external MOSFET turns on.