Abstract: A shower head of a combinatorial spatial atomic layer deposition (CS-ALD) apparatus may be provided. The shower head of the CS-ALD apparatus may include a plurality of shower blocks. Each of shower blocks may include a plurality of unit modules. Each of the shower blocks and each of the unit modules may be controlled independently from each other. Each of the plurality of unit modules may include a source gas injection nozzle, a purge gas injection nozzle, a reactant gas injection nozzle, and exhaust areas between the injection nozzles. The plurality of shower blocks may be separated from each other. Gas injection areas of the injection nozzles may be separated from the exhaust area.

Abstract: A method of evaluating the quality of a thin film layer may include: forming the thin film layer on a substrate; applying a stress to the thin film layer; and evaluating the quality of the thin film layer. A device for evaluating the quality of the thin film layer may include a stress chamber for applying a stress to the thin film layer and a refractive index measuring unit for evaluating the quality of the thin film layer based on a rate of change of a refractive index.

Abstract: A method of evaluating the quality of a thin film layer may include: forming the thin film layer on a substrate; applying a stress to the thin film layer; and evaluating the quality of the thin film layer. A device for evaluating the quality of the thin film layer may include a stress chamber for applying a stress to the thin film layer and a refractive index measuring unit for evaluating the quality of the thin film layer based on a rate of change of a refractive index.

Abstract: Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor.

Abstract: Example embodiments relate to a method of fabricating a synapse memory device capable of being driven at a low voltage and realizing a multi-level memory. The synapse memory device includes a two-transistor structure in which a drain region of a first transistor including a memory layer and a first source region of a second transistor share a source-drain shared area. The synapse memory device is controlled by applying a voltage through the source-drain shared area. The memory layer includes a charge trap layer and a threshold switching layer, and may realize a non-volatile multi-level memory function.

Abstract: A shower head of a combinatorial spatial atomic layer deposition (CS-ALD) apparatus may be provided. The shower head of the CS-ALD apparatus may include a plurality of shower blocks. Each of shower blocks may include a plurality of unit modules. Each of the shower blocks and each of the unit modules may be controlled independently from each other. Each of the plurality of unit modules may include a source gas injection nozzle, a purge gas injection nozzle, a reactant gas injection nozzle, and exhaust areas between the injection nozzles. The plurality of shower blocks may be separated from each other. Gas injection areas of the injection nozzles may be separated from the exhaust area.

Abstract: A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.

Abstract: Provided are semiconductor devices and methods of manufacturing the same. A semiconductor device may include a source, a drain, a semiconductor element between the source and the drain, and a graphene layer that is provided on the source and the semiconductor element and is spaced apart from the drain. Surfaces of the source and the drain are substantially co-planar with a surface of the semiconductor element. The semiconductor element may be spaced apart from the source and may contact the drain. The graphene layer may have a planar structure. A gate insulating layer and a gate may be provided on the graphene layer. The semiconductor device may be a transistor. The semiconductor device may have a barristor structure. The semiconductor device may be a planar type graphene barristor.

Abstract: Organic photoelectronic devices and image sensors including the organic photoelectronic devices, include a first light-transmitting electrode at a side where light enters, a second light-transmitting electrode opposite to the first light-transmitting electrode, an active layer between the first and second light-transmitting electrodes, and an ultraviolet (UV) ray blocking layer on the first light-transmitting electrode, wherein the ultraviolet (UV) ray blocking layer includes at least one metal oxide having a light transmittance of less than or equal to about 75% for light of less than or equal to about 380 nm.

Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.

Abstract: A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.

Abstract: A method of manufacturing a semiconductor device using a metal oxide includes forming a metal oxide layer on a substrate, forming an amorphous semiconductor layer on the metal oxide layer, and forming a polycrystalline semiconductor layer by crystallizing the amorphous semiconductor layer using the metal oxide layer.

Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.

Abstract: A method of transferring graphene includes forming a sacrificial layer and a graphene layer sequentially on a first substrate, bonding the graphene layer to a target layer, and removing the sacrificial layer using a laser and separating the first substrate from the graphene layer.

Abstract: A structure includes a silicon substrate, a plurality of silicon rods on the silicon substrate, a silicon layer on the plurality of silicon rods, and a GaN substrate on the silicon layer.

Abstract: A method for forming a selective ohmic contact for a Group III-nitride heterojunction structured device may include forming a conductive layer and a capping layer on an epitaxial substrate including at least one Group III-nitride heterojunction layer and having a defined ohmic contact region, the capping layer being formed on the conductive layer or between the conductive layer and the Group III-nitride heterojunction layer in one of the ohmic contact region and non-ohmic contact region, and applying at least one of a laser annealing process and an induction annealing process on the substrate at a temperature of less than or equal to about 750° C. to complete the selective ohmic contact in the ohmic contact region.

Abstract: A resistive memory device includes a first electrode and a first insulation layer arranged on the first electrode. A portion of the first electrode is exposed through a first hole in the first insulation layer. A first variable resistance layer contacts the exposed portion of the first electrode and extends on the first insulation layer around the first hole. A first switching device electrically connects to the first resistive switching layer.

Abstract: A method of transferring graphene includes forming a sacrificial layer and a graphene layer sequentially on a first substrate, bonding the graphene layer to a target layer, and removing the sacrificial layer using a laser and separating the first substrate from the graphene layer.

Abstract: A bonded substrate structure includes a siloxane-based monomer layer between a first substrate and a second substrate, the siloxane-based monomer layer bonding the first substrate and the second substrate. The first substrate and the second substrate may be one of a silicon substrate and a silicon oxide substrate, respectively.