Abstract: An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

Abstract: An LDMOS device and a method for forming the LDMOS device are provided. The LDMOS device includes: a substrate formed with a source region, a drain region and a drift region; a gate structure; a silicide block layer; a first conductive structure having one end electrically connected with the source region, a second conductive structure having one end electrically connected with the drain region; a first metal interconnecting structure electrically connected with the other end of the first conductive structure, a second metal interconnecting structure electrically connected with the other end of the second conductive structure; a third conductive structure having one end disposed on a surface of the silicide block layer; and a third metal interconnecting structure electrically connected with the other end of the third conductive structure. The LDMOS device has increased breakdown voltage, and reduced on-resistance, and its preparation process is safer and easier to control.

Abstract: A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.

Abstract: A method for manufacturing the semiconductor structure, including: providing a substrate including a first doping region, wherein a field oxide film is disposed on a top surface of the first doping region, a first pattern layer is disposed on a top surface of the field oxide film, and the first pattern layer exposes a portion of the top surface of the field oxide film; etching the field oxide film with the first pattern layer as a mask until a top surface of the substrate is exposed; forming a second doping region in the first doping region with the first pattern layer and the field oxide film as a mask; and forming a plurality of gate structures on a portion of a top surface of the second doping region, a spacer of the field oxide film and a portion of the top surface of the field oxide film.

Abstract: A split-gate flash memory, a method of fabricating the split-gate flash memory and a method for control thereof are disclosed. The split-gate flash memory includes: a semiconductor substrate including a first memory region and a second memory region that are separate from each other; and a word-line structure between the first memory region and the second memory region. The word-line structure includes, stacked on the surface of the semiconductor substrate sequentially from bottom to top, a word-line oxide layer, a read gate, a dielectric oxide layer and an erase gate. The read and erase gates can each function as a word line of the split-gate flash memory for enabling a read or erase operation. During the erase operation, a voltage applied on the erase gate has an insignificant impact on the underlying semiconductor substrate, which is helpful in reducing channel leakage in the semiconductor substrate.

Abstract: A method for manufacturing the semiconductor structure, including: providing a substrate including a first doping region, wherein a field oxide film is disposed on a top surface of the first doping region, a first pattern layer is disposed on a top surface of the field oxide film, and the first pattern layer exposes a portion of the top surface of the field oxide film; etching the field oxide film with the first pattern layer as a mask until a top surface of the substrate is exposed; forming a second doping region in the first doping region with the first pattern layer and the field oxide film as a mask; and forming a plurality of gate structures on a portion of a top surface of the second doping region, a spacer of the field oxide film and a portion of the top surface of the field oxide film.