Abstract: An interleaver generates a valid interleaved data address for each iteration i of the mapping by the interleaver without employing a multiplication operation. The interleaver includes an address generator comprises two counters, bit-reverse and index tables, and an accumulation register array. The interleaver further comprises two adders, two registers storing tentative address values addressi and addressi+1, and select logic including a comparator, two buffers, and a multiplexer (mux). Two counters are employed to allow the interleaver to generate at least one valid address for each iteration, and a tentative address is generated from each output value of the two counters. Each iteration generates an output interleaved address. A tentative address is generated by using a portion of the counter value as an address to select a corresponding entry from each of the bit-reverse and index tables and the accumulation register array.

Abstract: An iterative decoder decodes a frame of encoded data that includes error detection information, and terminates the iterative decoding based on a comparison of the decoded frame with the error detection information. The iterative decoder may have a maximum number of specified iterations, but may terminate the number of iterations early under specified conditions. The encoded data includes error detection information for parity check calculation. Error detection information may be in accordance with an error detection code, such as a cyclic redundancy check (CRC) code. After each iteration of decoding, a parity check is calculated for the decoded frame. Early termination of decoding may occur prior to an intermediate iteration threshold M of iterations when the parity check value of the decoded frame is equivalent to the parity check value calculated from the error detection information.

Abstract: An N-stage finite impulse response (FIR) filter embodying the invention includes a first filter section whose filter coefficients are made either 1 or zero (rather than 1 and −1) in order to produce a first output (i.e., C1) and a second filter section for producing a second output (i.e., C2), which when combined (added to or subtracted from) with the first output produces an output function (i.e., Cn) which is equal to that produced by an N-stage FIR filter implementing filter coefficients having a value of either 1 or −1.

Abstract: A methods comprising a hybrid early-termination strategy and an output selection procedure for iterative decoders are disclosed. The hybrid early-termination strategy combines the output-comparison-based method with the CRC-check-based method. The hybrid approach is far more superior in termination reliability in either of the two individual approaches, without their disadvantages. The hybrid termination strategy effectively and reliably terminates the iterative decoding process, cutting the majority of the computational load while eliminating the degradation in the bit error rate (BER) and frame-error-rate (FER) performance due to incorrectly terminated frames. The output selection procedure chooses the best possible decoded frame among those from all iterations, eliminating the iteration abnormality that is inherent in the iterative decoding approach, and improving the BER performance of the standard iterative decoders.

Abstract: The present invention discloses a device for generating multiple spreading sequences efficiently. In a preferred embodiment, the eight different spreading sequences are generated in parallel. In this embodiment, the spreading sequence generator comprises a master sequence generator and eight secondary sequence generators. The spreading sequence generator also comprises eight different modulo-2 adders which are used for generating parity check sum outputs. The master sequence generator is responsible for creating a master output from the first subgroup. The secondary sequence generators create eight different secondary outputs. Each of the secondary outputs is combined with the master output through one of the eight modulo-2 adders to create eight different spreading sequences. In an alternative embodiment, the principles of the present invention may be used to generate such spreading sequences in a sequential manner.

Abstract: A method of extracting an information bearing signal .omega.(n) from a base-band signal in the form of an inverse function with a digital signal processor. The processor includes memory and utilizes a minimum number of instructions stored in the memory. The base-band waveform comprises a plurality of complex-valued samples having respective I and Q components. The method includes the steps of receiving a first sample at an instant n having respective I(n) and Q(n) components and defining an interval for evaluating potential values for the I(n) and Q(n) components. Next, a step of transforming said I(n) and Q(n) components is performed to have respective threshold values residing in the predefined interval. Then, a step of estimating the transformed components with a series of non-inverted polynomial functions is carried out over the predefined interval.