Abstract: A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage including high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit including a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal, wherein a large inrush current flowing into the output capacitor when the circuit is starting up is minimized.

Abstract: A dead-time generator for incorporation in an integrated circuit wherein the integrated circuit includes a high side and low side gate driver and wherein the high side and low side gate driver drive output switches such that a dead-time is provided between on times of the output switches, the dead-time generator comprising a circuit internal to the integrated circuit having an external terminal at which a dead-time setting component is connected, and wherein the dead-time generator comprises a circuit for providing a discrete dead-time for a range of dead-time setting values at the dead-time setting terminal and wherein, for a plurality of ranges of dead-time setting values at the dead-time setting terminal, the dead-time generator generates an associated plurality of discrete dead-times.

Abstract: A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches. The circuit includes a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles; wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition where false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

Abstract: An apparatus and method for determining the output current in a bridge-connected switched transistor output circuit including high-side and low-side transistor switches, typically MOSFETS. The voltage at a common node between the high and low side switches is sensed, and offset in a first circuit by a fixed amount so that the voltage is positive for all positive or negative output currents of interest. The output current is actually determined in a second circuit which receives the offset voltage signal only predetermined times in relation to the on-time of the low side switch. The first circuit includes a current reference source/level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration. The second circuit is coupled to an output of the first circuit by a gated NMOS transistor at the desired times to provide the current measurement signal.

Abstract: An integrated noise isolation circuit on a single silicon substrate die having a structural arrangement that minimizes noise. The integrated circuit including a noise sensitive circuit including an input stage; a noise generating circuit including an output stage; at least one high voltage level shift circuit coupling the noise generating and noise sensitive circuits for transferring a signal from the input to the output stage; and at least one floating structure for isolating influence of the noise.

Abstract: A method for providing a soft start operation for a transistor driver circuit, comprising providing a saw tooth waveform from an oscillator at a given frequency; comparing the saw tooth waveform to a reference value; and modifying the saw tooth waveform as a result of the comparison to produce pulses of increased length when the reference value is below a value of the saw tooth waveform.

Abstract: A driver circuit for a transistor provides a soft start feature where pulses provided to the transistor are varied in duration during startup. The driver also provides an overcurrent protection feature for disabling a driver output for a safe period of time when an overcurrent condition is detected. The driver circuit includes an oscillator that produces a saw tooth wave and a narrow width pulse train for determining pulse width and dead time, respectively. The driver circuit may be used in half-bridge or full-bridge drivers.

Abstract: An integrated noise isolation circuit on a single silicon substrate die having a structural arrangement that minimizes noise. The integrated circuit including a noise sensitive circuit including an input stage; a noise generating circuit including an output stage; at least one high voltage level shift circuit coupling the noise generating and noise sensitive circuits for transferring a signal from the input to the output stage; and at least one floating structure for isolating influence of the noise.

Abstract: A circuit for minimizing voltage inrush upon startup in a switching power converter having a switching stage including high and low switches connected at a common node, a feedback loop for maintaining a target output voltage, an output capacitor connected between an output node and the ground, an inductor connected between the common node and the output node, and a control circuit having a first error amplifier for providing a first signal based on a comparison of a reference voltage and voltage provided by the feedback loop, the control circuit including a level switch connected between the ground and the common node, the level switch being controlled in accordance with the first signal, wherein a large inrush current flowing into the output capacitor when the circuit is starting up is minimized.

Abstract: A circuit for providing over-current protection, the circuit including a gate driver circuit for controlling a bridge circuit including a half bridge stage having high and low switches. The circuit includes a feedback loop circuit for counting over-current indicators sensed during one or more consecutive PWM cycles; wherein when an over-current indicator is sensed, the low switch is turned OFF for duration of a first time period after which the low switch is turned back ON, to enable determination of an over-current condition where false noise signals are rejected thereby preventing circuit shutdowns due to false over-current condition.

Abstract: A control terminal driver IC for a switching circuit having series connected high and low side output transistors, an associated split power supply and a floating input, the gate drive IC, an exemplary, but non-limiting, example of which is a Class D audio amplifier. The IC includes an input circuit, a voltage to current converter connected to the input circuit, a level shifter formed in a mid well of the IC, which is operative to transfer the input signal to the low side without the need for a power supply input to the mid well, a current to voltage converter on the low side coupled to the level shifter; and an output circuit which is operative to generate control terminal drive signals for the high and low side transistors.

Abstract: A dead-time generator for incorporation in an integrated circuit wherein the integrated circuit includes a high side and low side gate driver and wherein the high side and low side gate driver drive output switches such that a dead-time is provided between on times of the output switches, the dead-time generator comprising a circuit internal to the integrated circuit having an external terminal at which a dead-time setting component is connected, and wherein the dead-time generator comprises a circuit for providing a discrete dead-time for a range of dead-time setting values at the dead-time setting terminal and wherein, for a plurality of ranges of dead-time setting values at the dead-time setting terminal, the dead-time generator generates an associated plurality of discrete dead-times.

Abstract: A control terminal driver circuit for a switching amplifier including a driver for each of a pair of output power transistors responsive to a PWM information signal. The circuit operates in response to an operating state signal indicating a start up condition for the amplifier to vary the amplitude of the drive pulses for the output transistors between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector is provided to detect a DC offset at amplifier output, and an error circuit responsive to an output of the DC offset detector controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.

Abstract: An apparatus and method for determining the output current in a bridge-connected switched transistor output circuit including high-side and low-side transistor switches, typically MOSFETS. The voltage at a common node between the high and low side switches is sensed, and offset in a first circuit by a fixed amount so that the voltage is positive for all positive or negative output currents of interest. The output current is actually determined in a second circuit which receives the offset voltage signal only predetermined times in relation to the on-time of the low side switch. The first circuit includes a current reference source/level shifter and a current mirror circuit formed of a plurality of transistors in a particular circuit configuration. The second circuit is coupled to an output of the first circuit by a gated NMOS transistor at the desired times to provide the current measurement signal.

Abstract: A control terminal driver circuit for a switching amplifier including a driver for each of a pair of output power transistors responsive to a PWM information signal. The circuit operates in response to an operating state signal indicating a start up condition for the amplifier to vary the amplitude of the drive pulses for the output transistors between a zero value and a maximum value for normal operation of the amplifier over a start up interval, and to reverse the process during a shut down interval. A DC offset detector is provided to detect a DC offset at amplifier output, and an error circuit responsive to an output of the DC offset detector controls the relative amplitude of the driver outputs during at least a portion of the start up interval to substantially eliminate the DC offset. Also disclosed is a switching amplifier including a control terminal driver circuit as described above.

Abstract: A control terminal driver IC for a switching circuit having series connected high and low side output transistors, an associated split power supply and a floating input, the gate drive IC, an exemplary, but non-limiting, example of which is a Class D audio amplifier. The IC includes an input circuit, a voltage to current converter connected to the input circuit, a level shifter formed in a mid well of the IC, which is operative to transfer the input signal to the low side without the need for a power supply input to the mid well, a current to voltage converter on the low side coupled to the level shifter; and an output circuit which is operative to generate control terminal drive signals for the high and low side transistors.

Abstract: A driver circuit for a transistor provides a soft start feature where pulses provided to the transistor are varied in duration during startup. The driver also provides an overcurrent protection feature for disabling a driver output for a safe period of time when an overcurrent condition is detected. The driver circuit includes an oscillator that produces a saw tooth wave and a narrow width pulse train for determining pulse width and dead time, respectively. The driver circuit may be used in half-bridge or full-bridge drivers.