Abstract: Semiconductor devices including a cathode layer, an anode layer, an active layer disposed between the cathode layer and the anode layer, wherein the active layer includes a perovskite layer, and a passivation layer disposed directly on a surface of the active layer between the cathode layer and the active layer, the passivation layer including a zwitterionic amino acid, such as valine or phenylalanine or other amino acid that passivates both cationic and anionic defects in the surface of the active layer.

Abstract: The present invention discloses an air fryer, which comprises a fryer housing, a first chamber and a second chamber, wherein the first chamber is communicated with the second chamber, a bottom of the first chamber is provided with an air exhaust and a top of the second chamber is provided with an air intake; a heating element, which is arranged in the second chamber; a cross flow fan, which is located in the second chamber, wherein the cross flow fan comprises an impeller with a horizontal axis, and when the cross flow fan is in operation, air passes through the air intake horizontally and exits the air exhaust horizontally. The air fryer disclosed in the present invention is able to enhance the thermal cycle efficiency and the food could be heated even, crispy and tasting good.

Abstract: Perovskite materials useful in the manufacture of photovoltaic cells are provided. The perovskite materials have the formula AB?0.5B?0.5X3 or A?0.5A?0.5B?0.5B?0.5X3, wherein A, A?, and A? are organic or inorganic cations, X is a halogen ion, B? is tin, and B? is germanium. Embodiments of the mixed tin and germanium halide perovskite materials possess a direct bandgap within the optimal range of 0.9-1.6 eV and have an optical absorption spectrum that is comparable to the state-of-the-art methylammonium lead iodide perovskites. The perovskite materials provided herein have been formulated to be lead-free.

Abstract: A program calling system includes a memory, an interface establishing unit, a detecting unit, and a calling unit. The memory stores functions for PCB layout design. Each function corresponds to a path and a name, and can be accessed via the corresponding path and name. The interface establishing unit establishes a user interface. The user interface includes a first area for displaying the names of the functions. A one to one relationship exists between the names and the paths of the functions. The detecting unit detects whether a calling signal is generated, and obtains a name of a to-be-called function when the calling signal is generated. The calling unit responds to the calling signal to obtain a path of the to-be-called function according to the name of the to-be-called function and the one to one relationship, and call the to-be-called function according to the obtained path and name.

Abstract: A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram.

Abstract: A computer aided design system comprises an interface creating module, a selecting module, a filling module and a measuring module. The interface module creates a user interface to display the design on the screen of the device with a plurality of to-be-checked patterns. The selecting module selects a pattern. The interface module further creates a parameter setting interface. The parameters comprises a predetermined width, the space value between the adjacent parallel filled lines and the rotation degree of the selected pattern. The filling module draws filled lines in the selected pattern according to the parameters. The measuring module detects whether the length of each filled line is at least the predetermined width value, if the length of the filled line is less than the predetermined width value, the dimension of the selected pattern is unqualified and the measuring module highlights the filled lines.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining the outline information, the boundary information, and the auxiliary line information, when a command for recording position information of points within each of the boundaries is input; obtaining position information of the points within each of the boundaries; setting corresponding height values as height limit of height restriction areas corresponding to the points within each of the boundaries.

Abstract: A computer-implemented method for component arrangement in a PCB layout device is provided. The device includes wiring diagrams. First, generates a PCB encapsulation diagram corresponding to the selected wiring diagram. Then, obtains the coordinates of each electronic component in the selected wiring diagram. Next, generates a prompt to prompt the user to select a reference point in the PCB encapsulation diagram. Then, obtains the coordinates of the reference point. Next, determines an abscissa difference and an ordinate difference between one component in the wiring diagram and the reference point. Then, determines the coordinates of each encapsulated component in the PCB encapsulation diagram according to the abscissa difference, the ordinate difference, and the coordinates of each electronic component in the wiring diagram. And last, moves each encapsulated component to the determined corresponding coordinates of each encapsulated component in the PCB encapsulation diagram.

Abstract: A method for merging polygons of a printed circuit board layout system is provided. The system generates PCB files according to the input wiring diagram, and generates polygons and records the profile attributes of each of the generated polygons. The method includes obtaining the profile attributes in response to user input. Then storing the obtained profile attributes and selecting two profile attributes. Then determining whether the polygons are overlapping and recording a new file attribute describing the shape of a new polygon of the two polygons combined shape excluding the lines indicating the overlapping portions of the two polygons. Finally, updating the opened PCB file with the new profile attribute if the polygons are overlapping. A related system is also provided.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining corresponding outlines of selected component and unselected components in response to a user selecting one component; obtaining the range value; generating a reference outline according to the obtained range value and outline of the selected component; performing an intersection operation according to the reference outline and outlines of the unselected components, and determining whether one component is associated within the reference outline; marking and displaying the outlines of the corresponding unselected components when the unselected components are associated within the reference outline.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: A computer aided design system comprises an interface creating module, a selecting module, a filling module and a measuring module. The interface module creates a user interface to display the design on the screen of the device with a plurality of to-be-checked patterns. The selecting module selects a pattern. The interface module further creates a parameter setting interface. The parameters comprises a predetermined width, the space value between the adjacent parallel filled lines and the rotation degree of the selected pattern. The filling module draws filled lines in the selected pattern according to the parameters. The measuring module detects whether the length of each filled line is at least the predetermined width value, if the length of the filled line is less than the predetermined width value, the dimension of the selected pattern is unqualified and the measuring module highlights the filled lines.

Abstract: A method for automatically checking signal areas includes: recording etching line information of etching lines which divide an internal plane of an opened PCB file into a plurality of signal areas, recording input signal names and positions where the input signal names are arranged, obtaining the outline information of the opened internal plane and the etching line information, obtaining position information of points within each signal areas according to the outline information and the etching line information, determining whether one signal area is associated with one input signal name, determining whether the one input signal name matches one standard signal name, and setting one input signal name as a name attribute of the signal area associated with the one input signal name if the one input signal name matches one standard signal name. A related PCB system is also provided.

Abstract: The present invention is a common location-based service adapter interface. The common location-based service adapter interface can include a uniform input interface through which location-based services can be requested using a uniform format which is independent of any specific formatting required by a particular service adapter configured to process the location-based services. The common location-based service adapter interface also can include a uniform output interface through which specifically formatted result sets can be formatted using the uniform format.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining the outline information, the boundary information, and the auxiliary line information, when a command for recording position information of points within each of the boundaries is input; obtaining position information of the points within each of the boundaries; setting corresponding height values as height limit of height restriction areas corresponding to the points within each of the boundaries.

Abstract: A method for managing error information of a printed circuit board layout system is provided. The system provides an error file recording names of all the errors to be displayed in wiring diagrams, generates wiring diagram files, outputs a first user interface showing one wiring diagram. Each of the wiring diagram files includes an attribute table for describing error information. The attribute table comprises the names and the set of coordinates. The method comprises obtaining the error file and the attribute table, outputting a second user interface comprising a first display area and a second display area, outputting the name in the first display area, analyzing the obtained attribute table to provide a classifying table. Then outputting one selected name and at least one set of coordinates corresponding to the one selected name in the second display area according to the classifying table. A related system is also provided.

Abstract: A program calling system includes a memory, an interface establishing unit, a detecting unit, and a calling unit. The memory stores functions for PCB layout design. Each function corresponds to a path and a name, and can be accessed via the corresponding path and name. The interface establishing unit establishes a user interface. The user interface includes a first area for displaying the names of the functions. A one to one relationship exists between the names and the paths of the functions. The detecting unit detects whether a calling signal is generated, and obtains a name of a to-be-called function when the calling signal is generated. The calling unit responds to the calling signal to obtain a path of the to-be-called function according to the name of the to-be-called function and the one to one relationship, and call the to-be-called function according to the obtained path and name.

Abstract: A printed circuit board layout system and a method thereof are provided. The method includes the following steps: obtaining corresponding outlines of selected component and unselected components in response to a user selecting one component; obtaining the range value; generating a reference outline according to the obtained range value and outline of the selected component; performing an intersection operation according to the reference outline and outlines of the unselected components, and determining whether one component is associated within the reference outline; marking and displaying the outlines of the corresponding unselected components when the unselected components are associated within the reference outline.

Abstract: A method for merging polygons of a printed circuit board layout system is provided. The system generates PCB files according to the input wiring diagram, and generates polygons and records the profile attributes of each of the generated polygons. The method includes obtaining the profile attributes in response to user input. Then storing the obtained profile attributes and selecting two profile attributes. Then determining whether the polygons are overlapping and recording a new file attribute describing the shape of a new polygon of the two polygons combined shape excluding the lines indicating the overlapping portions of the two polygons. Finally, updating the opened PCB file with the new profile attribute if the polygons are overlapping. A related system is also provided.

Abstract: A method for automatically checking signal areas includes: recording etching line information of etching lines which divide an internal plane of an opened PCB file into a plurality of signal areas, recording input signal names and positions where the input signal names are arranged, obtaining the outline information of the opened internal plane and the etching line information, obtaining position information of points within each signal areas according to the outline information and the etching line information, determining whether one signal area is associated with one input signal name, determining whether the one input signal name matches one standard signal name, and setting one input signal name as a name attribute of the signal area associated with the one input signal name if the one input signal name matches one standard signal name. A related PCB system is also provided.