Abstract: A simulation apparatus and method is provided for simulating complex high speed interconnects for which closed forms of the S-parameter are incorporated. Differential transmission lines are represented in a causal manner analytically using the 4-port S-parameter without concerns of passivity and stability. Difficult discontinuities of interconnect such as differential vias are represented in closed form and the present invention allows those interconnects to be characterized by 4-port S-parameter measurements or simulation. A complete method of combining causal transmission line models with discontinuities in cascade is provided.

Abstract: Method and system that test device sensitivity according to whether the device passes or fails when subjected to a test signal. The device may be repeatedly subjected to test signal at varying operating parameters in order to assess pass-fail threshold at which the device transitions from operating properly/improperly to operating improperly/properly.

Abstract: Method and system that test device sensitivity according to whether the device passes or fails when subjected to a test signal. The device may be repeatedly subjected to test signal at varying operating parameters in order to assess pass-fail threshold at which the device transitions from operating properly/improperly to operating improperly/properly.

Abstract: A method for making measurements using a vector network analyzer, and for multi-port S-parameter and T-parameter conversion includes a generalized T-matrix definition that facilitates the conversion between the S-parameters and the T-parameters for multi-port networks based on the well understood and mathematically simple 2-port relations. One contemplated approach generalizes all multi-port networks into two cases: balanced and unbalanced. Through careful selection of the T-matrix, the contemplated method extends 2-port symmetry to multi-port networks and provides an engineering implementable relationship between the S- and T-parameters for multi-port networks. This symmetry extension allows a practical means to cascade and de-embed such networks.

Abstract: The present invention relates to a via parasitics testing and extracting method for Gigabit multi-layered PCB boards. The method of the present invention is a unique test and extraction process that utilizes a TDR measurement and processes the output data therefrom externally. The testing aspect involves obtaining a TDR module waveform and obtaining a text file with output data, whereas the extraction aspect involves analysis of the data in the text file. This method can be used directly to ascertain a Gigabit via structure without the limitations that are imposed by the conventional methods discussed above, and has been theoretically proven to be highly accurate and much faster than any of the existing methods. The method of the present invention has the potential to be included as a built-in testing feature in high-speed TDR meters, and may also be used in order to design an optimized via.