Abstract: Disclosed are an equipment failure mode predetermination and residual life prediction coupling system and method. The equipment failure mode predetermination and residual life prediction coupling system realizes coupling of equipment failure mode predetermination and residual life prediction, continuous collection of health information of equipment, predetermination of the failure mode and prediction of the residual life based on the state of health of the equipment in operation monitored and perceived in real time by sensor sets.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof, including: a substrate; a plurality of transistors, arranged based on a first preset pattern; a plurality of transistor contact structures, corresponding to the transistors, the bottom portions of the transistor contact structures are arranged based on the first preset pattern, and top portions of which are arranged based on the shape of a regular hexagon; a plurality of memory cells, corresponding to the transistor contact structures, the memory cells are arranged based on the shape of a regular hexagon; and a plurality of memory contact structures, corresponding to the memory cells, the bottom portions of the memory contact structures are arranged based on the shape of a regular hexagon, top portions of which are arranged based on a second preset pattern, and the second preset pattern is different from the first preset pattern.

Abstract: A semiconductor device includes a first wafer, and a second wafer bonded with the first wafer and comprising a substrate and a device layer over the substrate. The first wafer is over the second wafer and includes memory arrays, array-base regions over the memory arrays, an isolation structure surrounding and insulating the array-base regions from one another, and bonding pads over the isolation structure. An array-base region of the array-base regions is connected with a memory array of the memory arrays. A bonding pad of the bonding pads is exposed.

Abstract: The disclosure relates to a method and a system for predicting the operation time of sparse matrix vector multiplication. The method comprises constructing a convolutional neural network comprising an input layer, a feature processing layer, a data splicing layer and an output layer for outputting prediction results. The method further comprises acquiring a plurality of groups of sparse matrices with known sparse matrix vector multiplication operation time as sample data, inputting the sample data into the convolutional neural network to train the convolutional neural network, and inputting the sparse matrix to be classified into the trained convolutional neural network to realize the prediction of the operation time of sparse matrix vector multiplication.

Abstract: A method for manufacturing a semiconductor structure includes the following: providing a substrate; forming an MTJ structure and a first mask structure in sequence on the substrate; performing a patterning process on the first mask structure to form a first pattern extending in a first direction; transferring the first pattern to the MTJ structure; forming a second mask structure on the MTJ structure; performing a patterning process on the second mask structure to form a second pattern extending in a second direction, the first direction intersecting the second direction and being not perpendicular to the second direction; and performing a patterning process on the MTJ structure by utilizing the second pattern to form a cellular MTJ array, the first pattern and the second pattern together forming a cellular pattern.

Abstract: Embodiments of three-dimensional (3D) memory devices formed by bonded semiconductor devices and methods for forming the same are disclosed. In an example, a method for forming a semiconductor device is disclosed. The method includes the following operations. First, an insulating material layer can be formed over a substrate. In an example, single-crystalline silicon is not essential to the substrate. The insulating material layer can be patterned to form an isolation structure and a plurality of trenches in the isolation structure. A semiconductor material can be deposited to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another. Further, a plurality of memory arrays can be formed over the plurality of array-base regions, and an insulating structure can be formed to cover the plurality of memory arrays and the plurality of array-base regions.

Abstract: Embodiments of the present invention provide a storage cell and a data read/write method and storage array thereof. The storage cell includes a bit line, a tunnel junction, and four access transistors. Each access transistor includes at least an active region. The active region includes a source. The sources of the access transistors are all electrically connected to a first end of the tunnel junction. A second end of the tunnel junction is electrically connected to the bit line, and the bit line extends along a first direction. The active regions of the access transistors are isolated from one another. Long-side extension directions of the active regions of the access transistors are the same, and a first angle ? is formed between the long-side extension directions of the active regions and the first direction; wherein ? is a non-right angle.

Abstract: A semiconductor structure comprises: a substrate; a first transistor including a first gate located in the substrate and a first terminal located on a surface of the substrate, the first terminal being configured to be connected to a first-type memory cell; and a second transistor including a second gate located in the substrate and a second terminal located on the surface of the substrate, the second terminal being configured to be connected to a second-type memory cell, and a width of the second gate being less than a width of the first gate.

Abstract: The present disclosure provides a memory array, a memory cell, and a data read and write method thereof. Two storage nodes are provided in each memory cell of a memory array of a magnetic random access memory (MRAM), such that when one storage node in the memory cell fails, the other storage node in the memory cell can be used to write and read data.

Abstract: A method for coordinate error correction with a three-dimensional (3D) lidar scanner. The error source that affects the measurement accuracy of the three-dimensional coordinate is determined by building an error model, and then the error is modified to improve the measurement accuracy of the three-dimensional lidar scanner. The error correction method includes: building a theoretical calculation model, analyzing the source of measurement error, building an error model, solving the error model and implementing coordinate correction. During building the error model, 26 error factors are considered to obtain a calculation expression of the three-dimensional Cartesian coordinate. The calculation expression includes the amount of errors, the azimuth angle, the pitch angle and the distance.

Abstract: A finish coat composition, including: 30˜60 parts by mass of film-forming resin, where the film-forming resin includes one or more of acrylic resins and polyurethane acrylate resins; 5˜20 parts by mass of acrylate monomer; 1˜10 parts by mass of photoinitiator; 0.5˜10 parts by mass of leveling agent; 0˜20 parts by mass of matting powder; and 20˜50 parts by mass of solvent. This application further provides a composite material, a middle frame of an electronic device. The finish coat composition according to this application can be crosslinked and cured under an action of ultraviolet light to form a finish coat having good reliability and bonding performance, which is used as a finish coat layer of the middle frame of an electronic device and the battery cover of an electronic device, and has good bonding performance with glue, thereby preventing a screen of the electronic device from falling off.

Abstract: Provided is a semiconductor structure, a memory cell and a memory array. An nT-MRAM can be realized by a relatively simple structure. Transistors connected to multiple MTJs are connected by connecting pads.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a transistor; a first phase change memory structure, a bottom electrode of the first phase change memory structure being electrically connected to a first terminal (source or drain) of the transistor; a second phase change memory structure, a top electrode of the second phase change memory structure being electrically connected to the first terminal of the transistor; a first bit line, electrically connected to a top electrode of the first phase change memory structure; and a second bit line, electrically connected to a bottom electrode of the second phase change memory structure.

Abstract: The present disclosure provides a defect detection method and apparatus for a cushion layer of a cable, a device, and a storage medium. The method includes: obtaining specification parameters of a corrugated sheath of a to-be-detected cable, calculating a first volume of a cushion layer without deformation and a second volume of a deformed portion of the cushion layer when the cushion layer is deformed under stress, and calculating a stressed-state deformation ratio of the cushion layer based on the first volume and the second volume; obtaining a voltage, a current, an electrode area, an electrode distance, and an initial electrode distance of the cushion layer when the stressed-state deformation ratio is reached, and calculating volume resistivity of the cushion layer; and comparing the volume resistivity with a preset evaluation parameter to obtain a defect detection result of the cushion layer.

Abstract: The present application provides a magnetic memory and a reading/writing method thereof. The magnetic memory includes at least one cell layer, the cell layer including: a plurality of paralleled first conductors located in a first plane; a plurality of paralleled second conductors located in a second plane, the first plane being parallel to the second plane, a projection of the second conductor on the first plane intersecting with the first conductor; a plurality of memory elements arranged between the first plane and the second plane, the memory element including a magnetic tunnel junction and a bidirectional gating device arranged in series along a direction perpendicular to the first plane, the magnetic tunnel junction being connected to the first conductor, the bidirectional gating device being connected to the second conductor, and the bidirectional gating device being configured to be turned on when a threshold voltage and/or a threshold current are/is applied.

Abstract: The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor, including a first channel region disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; and a second transistor, including a second channel region disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the first channel region and the second channel region having different areas.

Abstract: The present application relates to a semiconductor structure and its forming method. The semiconductor structure comprises a substrate; a first transistor that includes a first channel disposed within the substrate, and a first end disposed at surface of the substrate, the first end being adapted to connect with a first-type storage cell; a second transistor that includes a second channel disposed within the substrate, and a second end disposed at surface of the substrate, the second end being adapted to connect with a second-type storage cell, the second channel having a length greater than length of the first channel. The present application enables fabrication techniques of the first transistor and the second transistor compatible. Moreover, the present application is conducive to enhancing integration density of the storage cells of the first transistor and/or the second transistor in the memory lays foundation for enlarging the fields of application of the memory.

Abstract: A quantum device includes: a quantum chip, provided with an I/O port; and a superconducting substrate, provided with transmission lines on the superconducting substrate. Each of the transmission lines includes a first section and a second section that form an included angle, a bonding connection structure is formed between one end of the first section and the I/O port, a pad for connecting to a connector is formed at one end of the second section, and a distribution spacing between the first sections is smaller than a distribution spacing between the second sections. The second sections are distributed in a region away from the quantum chip. The first section connected to the 1/0 port via aluminum wire bonding can be wired at higher density. The size of the pad on a wiring spacing is reduced, and density of the transmission lines on the superconducting substrate is increased.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a substrate; a transistor, including a control terminal, a first terminal, and a second terminal; a first magnetic memory structure, a bottom electrode of which is electrically connected to the first terminal of the transistor; a second magnetic memory structure, a top electrode of which is electrically connected to the first terminal of the transistor, the bottom electrode of the first magnetic memory structure is located in a same layer with a bottom electrode of the second magnetic memory structure; a first bit line, electrically connected to a top electrode of the first magnetic memory structure; a second bit line, electrically connected to the bottom electrode of the second magnetic memory structure; and a selection line, electrically connected to a second terminal of the transistor.

Abstract: Disclosed herein are liquid crystal-infused porous surfaces and methods of making and use thereof.