Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a multilayer cap layer and an ILD layer. A metal-filled via extends through the ILD layer and partially through the cap layer to make contact with the wiring line. There is a reliability enhancement material formed in one of the layers of the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line, a cap layer and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material in the cap layer. The reliability enhancement material surrounds the metal-filled via only in the cap layer to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress, wherein the compressive reliability enhancement material has different physical properties than the cap layer. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.

Abstract: A contact structure and assembly for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

Abstract: An method including forming multiple interconnect levels on top of one another, each level comprising a metal interconnect and a crack stop both embedded in a dielectric layer, and a dielectric capping layer directly on top of the dielectric layer and directly on top of the metal interconnect, the crack stop is an air gap which intersects an interface between the dielectric layer and the dielectric capping layer of each interconnect level, and forming a through substrate via through the multiple interconnect levels adjacent to, but not in direct contact with, the crack stop, the crack stop of each interconnect level is directly between the metal interconnect of each interconnect level and the through substrate via to prevent cracks caused during fabrication from propagating away from the through substrate via and damaging the metal interconnect.

Abstract: A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line; forming an interlayer dielectric (ILD) layer on the wiring line; forming a via opening through the ILD layer and reliability enhancement material to expose a surface of the wiring line; and filling the via opening with a metal to form a metal-filled via in contact with the wiring line wherein the reliability enhancement material is in direct contact with the metal-filled via; wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line. Another embodiment includes the metal-filled via being an iso-via so that there is only one metal-filled via per wiring line.

Abstract: A contact structure and assembly for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

Abstract: A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Abstract: A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

Abstract: Bilayer platelet fillers are employed to compensate for a positive coefficient of thermal expansion (CTE) of an embedding polymeric material, or even to provide a composite structure having a negative CTE to eliminate or alleviate thermomechanical stress and/or delamination during thermal cycling. A bilayer platelet includes two joined layers having different CTEs. The CTE mismatch induces bending of the bilayer platelets, thereby causing cavities at temperatures lower than the joining temperature at which the bilayers are joined. The decrease in the volume of the polymeric material and the bilayer platelets at low temperatures is compensated by an accompanying increase in the volume of the cavities so that the composite structure has a temperature independent volume, a low net CTE, or even a negative CTE.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

Abstract: A spalling method is provided that includes depositing a stressor layer on surface of a base substrate, and contacting the stressor layer with a planar transfer. The planar transfer surface is then traversed along a plane that is parallel to and having a vertical offset from the upper surface of the base substrate. The planar transfer surface is traversed in a direction from a first edge of the base substrate to an opposing second edge of the base substrate to cleave the base substrate and transfer a spalled portion of the base substrate to the planar transfer surface. The vertical offset between the plane along which the planar transfer surface is traversed and the upper surface of the base substrate is a fixed distance. The fixed distance of the vertical offset provides a uniform spalling force. A spalling method is also provided that includes a transfer roller.

Abstract: Methods for fabricating a back-end-of-line (BEOL) wiring structure, BEOL wiring structures, and design structures for a BEOL wiring structure. The BEOL wiring may be fabricated by forming a first wire in a dielectric layer and annealing the first wire in an oxygen-free atmosphere. After the first wire is annealed, a second wire is formed in vertical alignment with the first wire. A final passivation layer, which is comprised of an organic material such as polyimide, is formed that covers an entirety of a sidewall of the second wire.

Abstract: Bilayer platelet fillers are employed to compensate for a positive coefficient of thermal expansion (CTE) of an embedding polymeric material, or even to provide a composite structure having a negative CTE to eliminate or alleviate thermomechanical stress and/or delamination during thermal cycling. A bilayer platelet includes two joined layers having different CTEs. The CTE mismatch induces bending of the bilayer platelets, thereby causing cavities at temperatures lower than the joining temperature at which the bilayers are joined. The decrease in the volume of the polymeric material and the bilayer platelets at low temperatures is compensated by an accompanying increase in the volume of the cavities so that the composite structure has a temperature independent volume, a low net CTE, or even a negative CTE.