Patents by Inventor Xiao-Jie Yuan

Xiao-Jie Yuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Patent number: 7724016
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: January 19, 2009
    Date of Patent: May 25, 2010
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • CHARACTERIZING CIRCUIT PERFORMANCE BY SEPARATING DEVICE AND INTERCONNECT IMPACT ON SIGNAL DELAY
    Publication number: 20090121737
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Application
    Filed: January 19, 2009
    Publication date: May 14, 2009
    Applicant: XILINX, INC.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Patent number: 7489152
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: August 3, 2006
    Date of Patent: February 10, 2009
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Publication number: 20060267618
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Application
    Filed: August 3, 2006
    Publication date: November 30, 2006
    Applicant: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael Hart, Zicheng Ling, Steven Young
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Patent number: 7109734
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: September 19, 2006
    Assignee: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael J. Hart, Zicheng G. Ling, Steven P. Young
  • Layout correction algorithms for removing stress and other physical effect induced process deviation
    Patent number: 7032194
    Abstract: A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.
    Type: Grant
    Filed: February 19, 2003
    Date of Patent: April 18, 2006
    Assignee: Xilinx, Inc.
    Inventors: Shih-Cheng Hsueh, Xiao-Jie Yuan, Daniel Gitlin
  • Characterizing circuit performance by separating device and interconnect impact on signal delay
    Publication number: 20050149777
    Abstract: An integrated circuit (IC) includes multiple embedded test circuits that all include a ring oscillator coupled to a test load. The test load either is a direct short in the ring oscillator or else is a interconnect load that is representative of one of the interconnect layers in the IC. A model equation is defined for each embedded test circuit, with each model equation specifying the output delay of its associated embedded test circuit as a function of Front End OF the Line (FEOL) and Back End Of the Line (BEOL) parameters. The model equations are then solved for the various FEOL and BEOL parameters as functions of the test circuit output delays. Finally, measured output delay values are substituted in to these parameter equations to generate actual values for the various FEOL and BEOL parameters, thereby allowing any areas of concern to be quickly and accurately identified.
    Type: Application
    Filed: December 18, 2003
    Publication date: July 7, 2005
    Applicant: Xilinx, Inc.
    Inventors: Xiao-Jie Yuan, Michael Hart, Zicheng Ling, Steven Young