Patents by Inventor Xiao Kang JIAO
Xiao Kang JIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12164883Abstract: A method includes retrieving a plurality of datasets from respective memory registers of a memory and storing the retrieved plurality of datasets in respective register portions of a first register. A dataset of data-processing coefficients are stored in a second register. First processing is applied using, as the first operand, a first sub-set of dataset elements stored in the first register, and using, as the second operand, the data-processing coefficients, obtaining a first result. Second processing is applied using, as the first operand, a second sub-set of dataset elements stored in the first register comprised in a second window having a size equal to the dataset size, and using, as the second operand, the replica of the dataset of data-processing coefficients, obtaining a second result. An output is generated based on the first and second results. The first and second processing may perform multiply accumulate (MAC) operations.Type: GrantFiled: March 16, 2021Date of Patent: December 10, 2024Assignee: STMICROELECTRONICS S.r.l.Inventors: Xiao Kang Jiao, Fabio Giuseppe De Ambroggi, Loris Luise
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Patent number: 11630671Abstract: A device includes a circular buffer, which, in operation, is organized into a plurality of subsets of buffers, and control circuitry coupled to the circular buffer. The control circuitry, in operation, receives a memory load command to load a set of data into the circular buffer. The memory load command has an offset parameter indicating a data offset and a subset parameter indicating a subset of the plurality of subsets into which the circular buffer is organized. The control circuitry responds to the command by identifying a set of buffer addresses of the circular buffer based on a value of the offset parameter and a value of the subset parameter, and loading the set of data into the circular buffer using the identified set of buffer addresses.Type: GrantFiled: January 21, 2022Date of Patent: April 18, 2023Assignees: STMICROELECTRONICS (BEIJING) R&D CO., LTD., STMICROELECTRONICS S.r.l.Inventors: Xiao Kang Jiao, Fabio Giuseppe De Ambroggi
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Publication number: 20210303267Abstract: A method includes retrieving a plurality of datasets from respective memory registers of a memory and storing the retrieved plurality of datasets in respective register portions of a first register. A dataset of data-processing coefficients are stored in a second register. First processing is applied using, as the first operand, a first sub-set of dataset elements stored in the first register, and using, as the second operand, the data-processing coefficients, obtaining a first result. Second processing is applied using, as the first operand, a second sub-set of dataset elements stored in the first register comprised in a second window having a size equal to the dataset size, and using, as the second operand, the replica of the dataset of data-processing coefficients, obtaining a second result. An output is generated based on the first and second results. The first and second processing may perform multiply accumulate (MAC) operations.Type: ApplicationFiled: March 16, 2021Publication date: September 30, 2021Inventors: Xiao Kang JIAO, Fabio Giuseppe DE AMBROGGI, Loris LUISE
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Patent number: 10970192Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.Type: GrantFiled: March 28, 2019Date of Patent: April 6, 2021Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTDInventors: Xiao Kang Jiao, PengFei Zhu
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Patent number: 10783083Abstract: A cache memory is organized into a plurality of ways and a plurality of address lines. In response to a miss, the cache memory selects a way of the plurality of ways based on a first control variable indicating a way of the plurality of ways and a set of second control variables associated with the address line and with respective ways. Data associated with the miss is written to the selected way. Second control variables associated with other ways are reset if all of the second control variables indicate the associated way was recently replaced. The second control variable associated with the selected way is set to indicate the selected way was recently replaced. The first control variable is set to indicate the selected way. Current values of the first control variable and of the set of second control variables are maintained in the event of a hit.Type: GrantFiled: February 5, 2019Date of Patent: September 22, 2020Assignee: STMICROELECTRONICS (BEIJING) RESEARCH & DEVELOPMENT CO. LTDInventor: Xiao Kang Jiao
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Publication number: 20190251031Abstract: A cache memory is organized into a plurality of ways and a plurality of address lines. In response to a miss, the cache memory selects a way of the plurality of ways based on a first control variable indicating a way of the plurality of ways and a set of second control variables associated with the address line and with respective ways. Data associated with the miss is written to the selected way. Second control variables associated with other ways are reset if all of the second control variables indicate the associated way was recently replaced. The second control variable associated with the selected way is set to indicate the selected way was recently replaced. The first control variable is set to indicate the selected way. Current values of the first control variable and of the set of second control variables are maintained in the event of a hit.Type: ApplicationFiled: February 5, 2019Publication date: August 15, 2019Inventor: Xiao Kang JIAO
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Publication number: 20190227905Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.Type: ApplicationFiled: March 28, 2019Publication date: July 25, 2019Inventors: Xiao Kang JIAO, PengFei ZHU
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Patent number: 10296441Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.Type: GrantFiled: July 6, 2016Date of Patent: May 21, 2019Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTDInventors: Xiao Kang Jiao, PengFei Zhu
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Patent number: 10114644Abstract: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle.Type: GrantFiled: July 26, 2016Date of Patent: October 30, 2018Assignee: STMICROELECTRONICS (BEIJING) R&D CO. LTDInventors: PengFei Zhu, Xiao Kang Jiao
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Publication number: 20170344375Abstract: A decoding logic method is arranged to execute a zero-overhead loop in an embedded digital signal processor (DSP). In the method, instruction data is fetched from a memory, and a plurality of instruction tokens, which are derived from the instruction data, are stored in a token buffer. A first portion of one or more instruction tokens from the token buffer are passed to a first decode module, which may be an instruction decode module, and a second portion of the one or more instruction tokens from the token buffer are passed to a second decode module, which may be a loop decode module. The second decode module detects a special loop instruction token, and based on the detection of the special loop instruction token, a loop counter is conditionally tested. Using the first decode module, at least one instruction token of an iterative algorithm is assembled into a single instruction, which is executable in a single execution cycle.Type: ApplicationFiled: July 26, 2016Publication date: November 30, 2017Inventors: PengFei ZHU, Xiao Kang JIAO
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Publication number: 20170322867Abstract: A debug-enabled processing device includes a processor, a communication transceiver circuit, and a debug support unit. The debug support unit has a plurality of dedicated debug registers to facilitate debugging a software program under execution by the processor. One of the plurality of debug registers is a control register having at least four bits, which are used to enable/disable a plurality of debugging operations. Others of the debug registers include a set of index registers that may be configured to pass data to and from the processor.Type: ApplicationFiled: July 6, 2016Publication date: November 9, 2017Inventors: Xiao Kang JIAO, PengFei ZHU