Abstract: Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.

Abstract: Full-chip scan data can be advantageously used during design planning to minimize top-level scan wires and scan feedthroughs. The scan cells can be reordered using a modified cost function to promote connecting all scan cells in one plan group before crossing to a scan cell in another plan group. The modified cost function can take into account penalty parameters. The penalty parameters can include at least one of: membership in a plan group or a top-level physical hierarchy, size of a plan group, FLOATING/ORDERED scan element in scan data, location of endpoints of an ORDERED list, location of endpoints of a macro, and membership in a plan group containing a STOP point. Scan data, at the block-level and at the top-level, can be automatically updated to reflect the plan groups and optimized scan chains.

Abstract: A system and method performs signal net matching during delay routing. The delay router employs a region search for placing pseudo pins in a search region that will satisfy specified time delay constraints for a given signal net. The search region is an octagonal region defined by Manhattan detour lengths using derived wire length constraints as applied to a bounding box for the signal net. Any sequential router can be used to search the search region for free points. A first search phase finds delay paths to all free points in the search region from an arbitrary source pin. A second search phase then searches the search region for delay paths connecting a sink pin to one of the free points. Any delay path that connects the source and sink pin through a free point in the search region satisfies the time delay constraints. Dynamical routing can be implemented during the search phases as needed.