Abstract: A display panel includes an active area and a peripheral area surrounding the active area, and the display panel further includes: a substrate and a plurality of light emitting devices arranged on the substrate in array, wherein the plurality of light emitting devices are located at least in the active area; a conducting layer comprising a cathode ring and cathodes of the plurality of light emitting devices, wherein the cathode ring is located in the peripheral area, and the cathode ring surrounds the active area; and a lens layer located at a side of the light emitting devices away from the substrate, wherein the lens layer extends from the active area to the peripheral area; wherein an orthographic projection of the lens layer on the substrate is located within an area delineated by an outer contour of an orthographic projection of the cathode ring on the substrate.

Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

Abstract: A detector circuit included in a computer system filters the voltage level of a power supply node to generate filtered signals. The detector circuit either compares the filtered signals or samples the filtered signal and compares the samples to reference levels to detect changes in the voltage level of the power supply node that exceed thresholds for magnitude and duration. A control circuit included in the computer system generates, using the glitch signal, control signals that can be used to change operating parameters of functional circuits included in the computer system.

Abstract: Disclosed are a method and a system for controlling a photoelectric pod. The method for controlling the photoelectric pod includes: selecting one or more of three control modes: a mouse control, a touch screen control, and a joystick control according to current situation of the photoelectric pod for control operations.

Abstract: Methods and systems for generating an optimal clearance schedule for inventory items in a retail enterprise. A method includes accessing historical sales data for a plurality of inventory items in a department of a retailer. A selection of an item is received and a set of possible discount schedules for the item are generated. Each schedule includes a set of prices and a price duration. A forecasting tool provides a sales performance of the item based on the historical sales data. An optimal clearance schedule is selected from the possible discount schedules.

Abstract: A notch filter in a sigma-delta modulator loop filter increases SNR by limiting in-band quantization noise around a frequency to which the notch filter is precisely tuned. A tuning mode controller isolates the notch filter from other loop filter stages. A bias voltage is applied to the notch filter, causing it to resonate. Tuning mode switches insert the notch filter into a frequency-locked loop (“FLL”) circuit as a variable frequency oscillator component of the FLL. An ADC operational mode input signal is applied to the FLL as a reference signal. A tuning control component of the FLL adjusts a tunable feedback element in the notch filter to drive the FLL error signal to zero in order to precisely tune the notch filter to the center frequency of the ADC input signal. Tuning inputs to the tunable feedback element are then latched prior to re-inserting the notch filter into the modulator.

Abstract: A direct current (“DC”) calibration reference voltage is applied at an input terminal of an N-level sigma-delta analog-to-digital converter (“ADC”). The ADC includes a current-mode DAC (“I-DAC”) operating as a feedback element. A count of logical 1s associated with each of N output levels is taken at outputs of a modulator portion of the ADC during a first mismatch measurement interval. Mismatch measurement logic subsequently transposes pairs of current sources between level selection switch matrices. Doing so causes modulator output error components resulting from mismatches between I-DAC current sources (“delta”) to appear as differential level-specific output counts. The mismatch measurement logic compares the differential counts to determine values of delta. The ADC then factors decimated modulator output counts by values of delta in order to correct for the I-DAC current source mismatch(es).

Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

Abstract: A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.

Abstract: A voltage reference circuit includes a bipolar transistor and a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor. The output voltage of the voltage reference circuit is compensated as a function of the measured ratio.

Abstract: A temperature sensor uses a semiconductor device that has a known voltage drop characteristic that is proportional to absolute temperature (PTAT). A controllable current source is coupled to the semiconductor device and is operable to sequentially inject a bias current having a value I(bias) and fixed ratio N of I(bias) into the semiconductor device. A delta sigma analog to digital converter (ADC) has an input coupled to the semiconductor device. The delta sigma ADC is configured to sample and integrate a sequence of voltages pairs produced across the semiconductor device by repeatedly injecting an ordered sequence of selected bias currents into the semiconductor device. The ordered sequence of selected bias currents comprises M repetitions of (N×I(bias); I(bias)) and one repetition of (M×I(bias); M×N×I(bias)).

Abstract: A sealed composite bin for accommodating and delivering powder or particle material has multiple main bin units (11-13) arranged vertically and connected with each other, each including an arched main top part (111), a cylindrical main side wall (112) and a conical main bottom part (113). The radius of each main side wall is approximately the same, the in-line arrangement of the multiple main bin units (11-13) make the distance between the axes of the adjacent main bin units less than the sum of the radii of the two corresponding main side walls, and the multiple main bin units are communicated with each other. A supplementary bin unit (21) is provided between the adjacent main bin units, and the supplementary bin unit (21) includes a supplementary top part (211) connected to the top parts of the adjacent main bin units and cylindrical supplementary side walls (212,212?) connected to the side walls of the adjacent main bin units.

Abstract: An oscillator circuit and method for gain and phase noise control. A gain and phase noise controlled oscillator circuit includes a variable electronic oscillator and a tuning loop circuit. In operation, the variable electronic oscillator generates a clock signal and has a clock signal frequency that is controlled by a sense voltage received by the variable electronic oscillator or by one or more capacitive loads coupled to the variable electronic oscillator. Further, the tuning loop circuit is coupled to the variable electronic oscillator and compares the sense voltage to a control voltage received by the tuning loop circuit and produces one or more correction signals based on the comparison, where the one or more capacitive loads change capacitance based on the one or more correction signals.

Abstract: A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (gm) than if a single transistor were used while maintaining the same loop bandwidth and drain-to-source current through the transistor. As a result of a smaller transconductance in the VCO, a larger resistor can be used in the loop filter without increasing the noise. With a larger resistor, a smaller capacitor can be used in the loop filter as well. Alternatively, the transconductance can be reduced by a certain factor and the resistance value can be increased by the same factor to maintain a constant loop bandwidth but with a reduction in the amplitude of the noise. Thus, a smaller loop filter capacitor can be achieved albeit with the same noise level, or a lower noise level with the same size capacitor for the loop filter.

Abstract: An oscillator circuit and method for gain and phase noise control. A gain and phase noise controlled oscillator circuit includes a variable electronic oscillator and a tuning loop circuit. In operation, the variable electronic oscillator generates a clock signal and has a clock signal frequency that is controlled by a sense voltage received by the variable electronic oscillator or by one or more capacitive loads coupled to the variable electronic oscillator. Further, the tuning loop circuit is coupled to the variable electronic oscillator and compares the sense voltage to a control voltage received by the tuning loop circuit and produces one or more correction signals based on the comparison, where the one or more capacitive loads change capacitance based on the one or more correction signals.

Abstract: A phase-locked loop includes a loop filter and a voltage controlled oscillator (VCO). The VCO includes multiple transistors, each transistor having a smaller transconductance (gm) than if a single transistor were used while maintaining the same loop bandwidth and drain-to-source current through the transistor. As a result of a smaller transconductance in the VCO, a larger resistor can be used in the loop filter without increasing the noise. With a larger resistor, a smaller capacitor can be used in the loop filter as well. Alternatively, the transconductance can be reduced by a certain factor and the resistance value can be increased by the same factor to maintain a constant loop bandwidth but with a reduction in the amplitude of the noise. Thus, a smaller loop filter capacitor can be achieved albeit with the same noise level, or a lower noise level with the same size capacitor for the loop filter.

Abstract: A sealed composite bin for accommodating and delivering powder or particle material has multiple main bin units (11-13) arranged vertically and connected with each other, each including an arched main top part (111), a cylindrical main side wall (112) and a conical main bottom part (113). The radius of each main side wall is approximately the same, the in-line arrangement of the multiple main bin units (11-13) make the distance between the axes of the adjacent main bin units less than the sum of the radii of the two corresponding main side walls, and the multiple main bin units are communicated with each other. A supplementary bin unit (21) is provided between the adjacent main bin units, and the supplementary bin unit (21) includes a supplementary top part (211) connected to the top parts of the adjacent main bin units and cylindrical supplementary side walls (212,212?) connected to the side walls of the adjacent main bin units.