Patents by Inventor Xiao Teng

Xiao Teng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10943039
    Abstract: An example multiply accumulate (MACC) circuit includes: a multiply-accumulator having an accumulator output register; a quantizer, coupled to the multiply accumulator; and a control circuit coupled to the multiply-accumulator and the quantizer, the control circuit configured to provide control data to the quantizer, the control data indicative of a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: March 9, 2021
    Assignee: XILINX, INC.
    Inventors: Ashish Sirasao, Elliott Delaye, Sean Settle, Zhao Ma, Ehsan Ghasemi, Xiao Teng, Aaron Ng, Jindrich Zejda
  • Patent number: 10936311
    Abstract: Disclosed approaches for multiplying a sparse matrix by dense a vector or matrix include first memory banks for storage of column indices, second memory banks for storage of row indices, and third memory banks for storage of non-zero values of a sparse matrix. A pairing circuit distributes an input stream of vector elements across first first-in-first-out (FIFO) buffers according to the buffered column indices. Multiplication circuitry multiplies vector elements output from the first FIFO buffers by corresponding ones of the non-zero values from the third memory banks, and stores products in second FIFO buffers. Row-aligner circuitry organize the products output from the second FIFO buffers into third FIFO buffers according to row indices in the second memory banks. Accumulation circuitry accumulates respective totals from products output from the third FIFO buffers.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: March 2, 2021
    Assignee: Xilinx, Inc.
    Inventors: Ling Liu, Yifei Zhou, Xiao Teng, Ashish Sirasao, Chuanhua Song, Aaron Ng
  • Patent number: 10678509
    Abstract: An example multiply accumulate (MACC) circuit includes a multiply-accumulator having an accumulator output register, a scaler, coupled to the multiply accumulator, and a control circuit coupled to the multiply-accumulator and the scaler. The control circuit is configured to provide control data to the scaler, the control data indicative of: a most-significant bit (MSB) to least significant bit (LSB) range for selecting bit indices from the accumulator output register for implementing a first right shift; a multiplier; and a second right shift.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 9, 2020
    Assignee: XILINX, INC.
    Inventors: Sean Settle, Elliott Delaye, Aaron Ng, Ehsan Ghasemi, Ashish Sirasao, Xiao Teng, Jindrich Zejda
  • Publication number: 20190114534
    Abstract: At least one neural network accelerator performs operations of a first subset of layers of a neural network on an input data set, generates an intermediate data set, and stores the intermediate data set in a shared memory queue in a shared memory. A first processor element of a host computer system provides input data to the neural network accelerator and signals the neural network accelerator to perform the operations of the first subset of layers of the neural network on the input data set. A second processor element of the host computer system reads the intermediate data set from the shared memory queue, performs operations of a second subset of layers of the neural network on the intermediate data set, and generates an output data set while the neural network accelerator is performing the operations of the first subset of layers of the neural network on another input data set.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Xilinx, Inc.
    Inventors: Xiao Teng, Aaron Ng, Ashish Sirasao, Elliott Delaye
  • Publication number: 20190114529
    Abstract: In the disclosed methods and systems for processing in a neural network system, a host computer system writes a plurality of weight matrices associated with a plurality of layers of a neural network to a memory shared with a neural network accelerator. The host computer system further assembles a plurality of per-layer instructions into an instruction package. Each per-layer instruction specifies processing of a respective layer of the plurality of layers of the neural network, and respective offsets of weight matrices in a shared memory. The host computer system writes input data and the instruction package to the shared memory. The neural network accelerator reads the instruction package from the shared memory and processes the plurality of per-layer instructions of the instruction package.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Xilinx, Inc.
    Inventors: Aaron Ng, Elliott Delaye, Ehsan Ghasemi, Xiao Teng, Jindrich Zejda, Yongjun Wu, Sean Settle, Ashish Sirasao
  • Publication number: 20190114533
    Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator using a library. The neural network application may execute on a host computing system while the neural network accelerator executes on a massively parallel hardware system, e.g., a FPGA. The library operates a pipeline for submitting the tasks received from the neural network application to the neural network accelerator. In one embodiment, the pipeline includes a pre-processing stage, an FPGA execution stage, and a post-processing stage which each correspond to different threads. When receiving a task from the neural network application, the library generates a packet that includes the information required for the different stages in the pipeline to perform the tasks. Because the stages correspond to different threads, the library can process multiple packets in parallel which can increase the utilization of the neural network accelerator on the hardware system.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Xilinx, Inc.
    Inventors: Aaron Ng, Jindrich Zejda, Elliott Delaye, Xiao Teng, Sonal Santan, Soren T. Soe, Ashish Sirasao, Ehsan Ghasemi, Sean Settle
  • Publication number: 20190114535
    Abstract: A disclosed neural network processing system includes a host computer system, a RAMs coupled to the host computer system, and neural network accelerators coupled to the RAMs, respectively. The host computer system is configured with software that when executed causes the host computer system to write input data and work requests to the RAMS. Each work request specifies a subset of neural network operations to perform and memory locations in a RAM of the input data and parameters. A graph of dependencies among neural network operations is built and additional dependencies added. The operations are partitioned into coarse grain tasks and fine grain subtasks for optimal scheduling for parallel execution. The subtasks are scheduled to accelerator kernels of matching capabilities. Each neural network accelerator is configured to read a work request from the respective RAM and perform the subset of neural network operations on the input data using the parameters.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 18, 2019
    Applicant: Xilinx, Inc.
    Inventors: Aaron Ng, Jindrich Zejda, Elliott Delaye, Xiao Teng, Ashish Sirasao
  • Publication number: 20150256441
    Abstract: Embodiments of the present invention provide a neighbor relationship processing method and a routing device. The method includes: receiving, by a first routing device, a packet that is sent by a second routing device and used for requesting establishment of a neighbor relationship; determining, by the first routing device, whether the first routing device and the second routing device are both non-designated routing devices DRothers; and if the first routing device determines that the first routing device and the second routing device are both DRothers, discarding, by the first routing device, the packet used for requesting establishment of a neighbor relationship. According to the present invention, when the first routing device and the second routing device are both DRothers, the packet used for requesting establishment of a neighbor relationship is discarded, which reduces the number of neighbors maintained by the first routing device.
    Type: Application
    Filed: May 19, 2015
    Publication date: September 10, 2015
    Inventors: Qiangzhou Gao, Xiao Teng
  • Publication number: 20050261593
    Abstract: Disclosed is a method for measuring an arterial blood pressure of a subject comprising detecting a pulse-wave-related signal of the subject; extracting a feature from the signals; determining a factor that can affect the arterial blood pressure of the subject; and determining the arterial blood pressure based on the feature with an automatic compensation for the factors. The disclosed method reduces the error in measuring the blood pressure based on characteristics of the pulse-wave-related signals.
    Type: Application
    Filed: May 20, 2005
    Publication date: November 24, 2005
    Inventors: Yuan Zhang, Lung Yip, Xiao Teng, Chung Yan Poon, Chi Lee