Abstract: Methods and apparatus are provided for communicating a message to multiple radio groups (102, 104). An exemplary method (300) involves configuring, by an initiating radio device (120), a header portion of a message (308) for a multi-group communication session including the plurality of radio groups (102, 104) and transmitting the message (310). Each respective radio device (110) of each respective radio group (102, 104) is configured to provide output (408) corresponding to a content portion of the message in response to identifying its own radio group (406) in the header portion of the message (404).

Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. Thus, data that otherwise may be evicted or demoted, but that meets or exceeds the utility metric threshold, is exempted from space reclamation and is instead maintained in the data storage memory.

Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache, including considering an Input/Output Performance (IOP) metric, a bandwidth metric, and a garbage collection metric, and a whole data segment is promoted containing the one of the partial data segments to both the lower and higher levels of cache.

Abstract: A method for managing cache memories includes providing a computerized system including a shared data storage system (CS) configured to interact with several local servers that serve applications using respective cache memories, and access data stored in the shared data storage system; providing cache data information from each of the local servers to the shared data storage system, the cache data information comprising cache hit data representative of cache hits of each of the local servers, and cache miss data representative of cache misses of each of the local servers; aggregating, at the shared data storage system, at least part of the cache hit and miss data received and providing the aggregated cache data information to one or more of the local servers; and at the local servers, updating respective one or more cache memories used to serve respective one or more applications based on the aggregated cache data information.

Abstract: An apparatus and method for a memory controller for managing scheduling requests in a solid state memory device. The memory includes a set of units wherein a unit within the set of units is erasable as a whole by a unit reclaiming process resulting in a free unit available for writing data to. The memory controller further includes a first queue for queuing user requests for reading and/or writing data from/to the memory, and a second queue for queuing unit reclaiming requests for executing the unit reclaiming process. A scheduler is provided for selecting user requests from the first queue and unit reclaiming requests from the second queue for execution according to a defined ratio. The defined ratio is a variable ratio, is dependent on the current number of free units, and permits the memory controller to select requests from both the first queue and the second queue.

Abstract: A method for managing cache memory in a flash cache architecture. The method includes providing a storage cache controller, at least a flash memory comprising a flash controller, and at least a backend storage device, and maintaining read cache metadata for tracking on the flash memory cached data to be read, and write cache metadata for tracking on the flash memory data expected to be cached.

Abstract: A system including transmission lines, read elements, and differential amplifiers. The read elements are connected in series. Each of the read elements is connected to a respective pair of the transmission lines. The differential amplifiers are connected respectively to the read elements via the transmission lines. The differential amplifiers are configured to amplify differential signals received from the respective pairs of the transmission lines.

Abstract: For movement of partial data segments within a computing storage environment having lower and higher levels of cache by a processor, a whole data segment containing one of the partial data segments is promoted to both the lower and higher levels of cache. Requested data of the whole data segment is split and positioned at a Most Recently Used (MRU) portion of a demotion queue of the higher level of cache.

Abstract: An apparatus and method for a memory controller for managing scheduling requests in a solid state memory device. The memory includes a set of units wherein a unit within the set of units is erasable as a whole by a unit reclaiming process resulting in a free unit available for writing data to. The memory controller further includes a first queue for queuing user requests for reading and/or writing data from/to the memory, and a second queue for queuing unit reclaiming requests for executing the unit reclaiming process. A scheduler is provided for selecting user requests from the first queue and unit reclaiming requests from the second queue for execution according to a defined ratio. The defined ratio is a variable ratio, is dependent on the current number of free units, and permits the memory controller to select requests from both the first queue and the second queue.

Abstract: Methods and apparatus are provided for controlling data management operations including storage of data in solid state storage of a solid state storage system. Input data is stored in successive groups of data write locations in the solid state storage. Each group comprises a set of write locations in each of a plurality of logical subdivisions of the solid state storage. The input data to be stored in each group is encoded in accordance with first and second linear error correction codes. The encoding is performed by constructing from the input data to be stored in each group a logical array of rows and columns of data symbols. The rows and columns are respectively encoded in accordance with the first and second linear error correction codes to produce an encoded array in which all rows correspond to respective first codewords and columns correspond to respective second codewords.

Abstract: Synthesis and characterization of starch based pH-responsive nanoparticles for controlled drug delivery are described. Polymethacrylic acid grafted starch (PMAA-g-St) nanoparticles with various molar ratio of starch to MAA were synthesized by a new one-pot method that enabled simultaneous grafting of PMAA and nanoparticle formation in an aqueous medium. NMR data showed that polysorbate 80 was polymerized into the graft polymer. Nanoparticles were relatively spherical with narrow size distribution and porous surface morphology and exhibited pH-dependent swelling in physiological pH range. The particle size and magnitude of volume phase transition were dependent on PMAA content and formulation parameters such as surfactant levels, cross-linker amount, and total monomer concentration. The results showed that the new pH-responsive nanoparticles possessed useful properties for controlled drug delivery.

Abstract: Controlling a process of an application in a computer system is described. A driving module in the computer system may control a process of a first application. The driving module may determine a memory space for the process of the first application, and inject instructions of a second application into the memory space. The driving module may trigger a first application module in the computer system to execute the process of the first application, which is injected with the instructions. The driving module may have a relatively high calling privilege and hence does not give rise to code injecting failures that may be faced by a low privilege application. Further, since the security of operations of the driving module may be determined by the driving module itself, the operation for injecting instructions may not be considered and intercepted as a potentially harmful operation.

Abstract: A system including a first transmission line, a second transmission line, a first element, a second element and a differential amplifier. The first element is configured to read a storage media to generate a read signal, where the first element is connected to the first transmission line. The second element is configured to detect interference and generate an interference signal, where the second element is connected to the second transmission line. The differential amplifier includes a first input and a second input, where the first input of the differential amplifier is connected to a the first transmission line and receives the read signal, and where the second input of the differential amplifier is connected to the second transmission line and receives the interference signal.

Abstract: A system including transmission lines, read elements, and differential amplifiers. The read elements are connected in series. Each of the read elements is connected to a respective pair of the transmission lines. The differential amplifiers are connected respectively to the read elements via the transmission lines. The differential amplifiers are configured to amplify differential signals received from the respective pairs of the transmission lines.

Abstract: A semiconductor package includes an interposer and a plurality of integrated circuit (IC) dice disposed on and intercoupled via the interposer. A first IC die has a clock speed rating that is greater than a clock speed rating of another of the IC dice. A plurality of programmable voltage tuners are coupled to the plurality of IC dice, respectively. A first voltage tuner is coupled to the first IC die, and the first voltage tuner is programmed to reduce a voltage level of voltage input to the first voltage tuner and output the reduced voltage to the first IC die.

Abstract: For efficient track destage in secondary storage in a more effective manner, for temporal bits employed with sequential bits for controlling the timing for destaging the track in a primary storage, a preference of movement to lower speed cache level is implemented based on at least one of an amount of holes and a data heat metric. If a first bit has at least one of a lower amount of holes and a hotter data heat metric, it is moved to the lower speed cache level ahead of a second bit that has at least one of a higher amount of holes and a cooler data heat. If the first bit has a hotter data heat and greater than a predetermined number of holes, the first bit is discarded.

Abstract: A connector is fixed in an opening of a housing of an electronic device. The connector comprises a main body housed in the opening, a gasket and a securing member. The main body comprises a plug portion, and an engaging portion connecting the plug portion. Furthermore, an engaging groove located on the engaging portion adjacent to the plug portion. The gasket located between the between the plug portion and the housing. The engaging portion sequentially passes through the gasket and the opening to make a part of the engaging groove away from the plug portion is located a side of the housing. The securing member partly engaged in the engaging groove and sandwiched between the engaging portion and the housing to fix the main body to the housing.

Abstract: A Flash memory controller is coupled to a first Flash memory package through a first Flash memory interface and to a second Flash memory package through the first Flash memory interface. The Flash memory controller is designed to receive a first instruction relating to the first Flash memory package and to perform a first process depending on the first instruction. The Flash memory controller is further designed to receive a second instruction relating to the second Flash memory package and to perform a second process depending on the second instruction. The Flash memory controller is further adapted for splitting the first process into at least two first sub-steps and for splitting the second process into at least two second sub-steps. The Flash memory controller is further adapted for executing the first and second sub-steps, and for interleaving execution of first and second sub-steps.

Abstract: A method, device, and a computer storage medium are provided. The method includes: starting a core file and building an environment after running an operation system, then loading a driver in the built environment; reading a configuration file by the driver to obtain a path of a malware; and deleting a registry and file of the malware in a kernel layer according to the path. The device includes: a start loading module configured to start a core file and build an environment after running an operation system, then load a driver in the built environment; a path reading module configured to calculate a configuration file by the driver to obtain a path of a malware; and a program deleting module configured to delete a registry and file of the malware in a kernel layer according to the path.

Abstract: A method for tracking an interposer die of a stacked silicon interconnect technology (SSIT) product includes forming a plurality of dummy components on the interposer die, and modifying one or more of the plurality of dummy components on the interposer die to form a unique identifier for the interposer die. An apparatus for a stacked silicon interconnect technology (SSIT) product includes an interposer die, and a plurality of dummy components at the interposer die. One or more of the plurality of dummy components is modifiable to form a unique identifier for the interposer die.