Patents by Inventor XIAOYUAN ZHI

XIAOYUAN ZHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10622253
    Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: April 14, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
  • Publication number: 20190378757
    Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Applicant: United Microelectronics Corp.
    Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
  • Publication number: 20190051666
    Abstract: A semiconductor device includes a substrate having a frontside and a backside. The substrate includes a semiconductor layer and a buried insulator layer. A transistor is disposed on the semiconductor layer. An interlayer dielectric (ILD) layer is disposed on the frontside and covering the transistor. A contact structure penetrates through the ILD layer, the semiconductor layer and the buried insulator layer. A silicide layer caps an end surface of the contact structure on the backside. A passive element is disposed on the backside of the substrate. The contact structure is electrically connected to the passive element.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 14, 2019
    Inventors: Wen-Shen Li, XIAOYUAN ZHI, XINGXING CHEN, Ching-Yang Wen