Patents by Inventor Xiaobing Lee

Xiaobing Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11556462
    Abstract: A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 17, 2023
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiangyu Tang, Ken Hu, Xiaobing Lee, Yunxiang Wu
  • Patent number: 11449445
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 20, 2022
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang
  • Publication number: 20200192841
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Application
    Filed: February 26, 2020
    Publication date: June 18, 2020
    Inventors: Xiaobing Lee, Feng Yang
  • Patent number: 10628343
    Abstract: A hybrid DDR5 DIMM device includes a PCB board with a host interface through one of two DDR5 sub-channels, and a plurality of DDR4 or slow DDR5 SDRAM chips on the PCB coupled to this single channel DDR5 host interface. An embodiment processing system includes a host CPU to access one or more pairs of hybrid DDR5 DIMM devices for 4×DDR5 memory capacities (4DPC), a first or second hybrid DDR5 DIMM including a plurality of half-speed SDRAM chips, and a first or second DDR5 sub-channel coupled the host with slow SRAM chips on DIMM. Mounting same data-buffer and RCD chips on hybrid DIMM to a server motherboard can double available DDR4 DIMMs' speed to DDR5 speed rate. Pairs of hybrid DDR5 DIMM devices cascaded one-by-one can aggregate more DDR5 DIMM devices to expand memory capacities at double speed of DDR4 or DDR5 SDRAM chips, beyond current DDR5 speed limit 6400 MT/s.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: April 21, 2020
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventor: Xiaobing Lee
  • Patent number: 10579560
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: March 3, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang
  • Patent number: 10453530
    Abstract: System and method for a unified memory and network controller for an all-flash array (AFA) storage blade in a distributed flash storage clusters over a fabric network. The unified memory and network controller has 3-way control functions including unified memory buses to cache memories and DDR4-AFA controllers, a dual-port PCIE interconnection to two host processors of gateway clusters, and four switch fabric ports for interconnections with peer controllers (e.g., AFA blades and/or chassis) in the distributed flash storage network. The AFA storage blade includes dynamic random-access memory (DRAM) and magnetoresistive random-access memory (MRAM) configured as data read/write cache buffers, and flash memory DIMM devices as primary storage. Remote data memory access (RDMA) for clients via the data caching buffers is enabled and controlled by the host processor interconnection(s), the switch fabric ports, and a unified memory bus from the unified controller to the data buffer and the flash SSDs.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Michael Young, Ting Li, Yansong Wang, Yong Chen
  • Patent number: 10453501
    Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 22, 2019
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang, Yu Meng, Yunxiang Wu
  • Publication number: 20190065237
    Abstract: Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.
    Type: Application
    Filed: October 30, 2018
    Publication date: February 28, 2019
    Inventors: Xiaobing Lee, Feng Yang, Shaojie Chen
  • Publication number: 20190012259
    Abstract: According to various aspects of the present disclosure, there is provided a method and an apparatus for writing and evicting data in a phase-change memory (PCM). In one embodiment, a logical block address (LBA) eviction candidate (LEC) list is stored in the PCM media. The LEC list employs a circular queue having a head end and tail end, where new LBAs are inserted at the head end. In one embodiment, a tail end LBA at the tail end of the LEC list along with all the subsequent LBAs on the LEC list with continuing write sequence number to that of the tail end LBA are evicted when data needs to be evicted from the PCM media.
    Type: Application
    Filed: July 6, 2017
    Publication date: January 10, 2019
    Inventors: Xiangyu Tang, Xiaobing Lee, Yunxiang Wu, Ken Hu
  • Patent number: 10127074
    Abstract: Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: November 13, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang, Shaojie Chen
  • Publication number: 20180225235
    Abstract: A hybrid DDR5 DIMM device includes a PCB board with a host interface through one of two DDR5 sub-channels, and a plurality of DDR4 or slow DDR5 SDRAM chips on the PCB coupled to this single channel DDR5 host interface. An embodiment processing system includes a host CPU to access a pairs of hybrid DDR5 DIMM devices for 4× DDR5 memory capacities (4DPC), a first or second hybrid DDR5 DIMM including a plurality of half-speed SDRAM chips, and a first or second DDR5 sub-channel coupled the host with slow SRAM chips on DIMM. Mounting same data-buffer and RCD chips on hybrid DIMM to a server motherboard can double available DDR4 DIMMs' speed to DDR5 speed rate. Pairs of hybrid DDR5 DIMM devices cascaded one-by-one can aggregate more DDR5 DIMM devices to expand memory capacities at double speed of DDR4 or DDR5 SDRAM chips, beyond current DDR5 speed limit 6400 MT/s.
    Type: Application
    Filed: February 3, 2017
    Publication date: August 9, 2018
    Inventor: Xiaobing Lee
  • Patent number: 10042565
    Abstract: A computer-implemented method for storing and caching data in an all-flash-array includes erasing a TLC-NAND flash cell and programming the cell with a binary value multiple times in sequence corresponding to multiple sequential stages between erasures. The method also includes processing the binary value in relation to a respective threshold voltage at each of the multiple sequential stages. The method further includes storing metadata corresponding to a current stage associated with the number of times the TLC-NAND flash cell has been programmed since being erased.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: August 7, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventor: Xiaobing Lee
  • Publication number: 20180219562
    Abstract: Various embodiments include methods and apparatus structured to provide synchronization of a transaction identification between a host and a memory module using a parity check. A transaction identification can be generated at both the host and the memory module independently using incremental counters of these apparatus. Synchronization of the transaction identifications generated by the host and by a controller of the memory module can be implemented using a parity bit sequences pattern of a combination of the generated transaction identification plus the corresponding transaction command and data address. Use of transaction commands modified with respect to transaction identifications can be used in initialization of the synchronization, in message passing, and in error detection and response to errors. Additional apparatus, systems, and methods can be implemented in a variety of applications.
    Type: Application
    Filed: January 27, 2017
    Publication date: August 2, 2018
    Inventors: Xiaobing Lee, Feng Yang, Shaojie Chen
  • Publication number: 20180197584
    Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
    Type: Application
    Filed: March 6, 2018
    Publication date: July 12, 2018
    Inventors: Xiaobing Lee, Feng Yang, Yu Meng, Yunxiang Wu
  • Patent number: 9940980
    Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: April 10, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Feng Yang, Yu Meng, Yunxiang Wu
  • Publication number: 20180059966
    Abstract: A transaction-based hybrid memory device includes a host memory controller to control operation of the device. A hybrid memory controller is coupled to the host memory controller over a memory bus. The hybrid memory controller includes non-volatile memory control logic to control operation of non-volatile memory devices and cache control logic to accelerate cache operations, a direct memory access (DMA) engine to control volatile cache memory and to transfer data between non-volatile memory, and cache memory to off load host cache managements and transactions. A host interface couples the host memory controller to the memory bus.
    Type: Application
    Filed: August 31, 2016
    Publication date: March 1, 2018
    Inventors: Xiaobing Lee, Feng Yang
  • Publication number: 20180060227
    Abstract: A method performed by a processor to improve wear-leveling in a cross-point (X3D) memory, comprises detecting, by a processor coupled to the X3D memory, a trigger event, wherein the X3D memory comprises a first section of memory units and a second section of memory units, and in response to detecting the trigger event, relocating, by the processor, data stored in a first memory unit of the first section of memory units to a memory unit adjacent to a last memory unit of the first section of memory units, and relocating, by the processor, data stored in a first memory unit of the second section of memory units to a memory unit adjacent to a last memory unit of the second section of memory units.
    Type: Application
    Filed: January 31, 2017
    Publication date: March 1, 2018
    Inventors: Xiangyu Tang, Ken Hu, Xiaobing Lee, Yunxiang Wu
  • Patent number: 9887008
    Abstract: As a solution to the type of problems noted above, this disclosure provides novel methods and systems that include dual-port solid-state drive (SSD) DIMM devices to provide primary storage capabilities with very low latency and better availability of DDR4 devices. The dual-port DDR4-SSD flash memory devices guarantee primary storage devices still accessible with one CPU or network failure. The novel DDR4 memory bus devices may be used not only for memory media and storage device buffers, but also to allow two CPUs to share data stored in flash SSD chips and to greatly improve DDR4 bus efficiency and bus utilizations by block accesses and eliminate PCIE-DMA data transfers. Through the features of the claimed subject matter described herein, dual-port DDR4-DIMM memory devices can be achieved that provide an All-Flash-Array storage system with substantially higher reliability, availability, and performance over conventional SATA/SAS-SSD, PCIE-SSD, and NVME-SSD solutions.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: February 6, 2018
    Assignee: Futurewei Technologies, Inc.
    Inventors: Xiaobing Lee, Yansong Wang, Ting Li
  • Publication number: 20180005670
    Abstract: An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in two or more DRAM die, wherein a portion of the DRAM is allocated as a cache memory for the NVM; and a hybrid controller for the NVM and DRAM. The hybrid controller includes an NVM interface to the NVM; a DRAM interface to the cache memory; a host interface to communicate data with a host processor, wherein the host interface includes a parallel data bus for reading and writing data directly with both of the DRAM and the NVM; and logic circuitry configured to interleave access by the host processor and hybrid controller to the DRAM and NVM.
    Type: Application
    Filed: June 30, 2016
    Publication date: January 4, 2018
    Inventors: Xiaobing Lee, Feng Yang, Yu Meng, Yunxiang Wu
  • Patent number: 9852779
    Abstract: A memory system is disclosed that includes a first FPGA controller coupled to a first SSD cluster, a first DDR4 DIMM and a second DDR4 DIMM. A second FPGA controller is coupled to a second SSD cluster, the first DDR4 DIMM and the second DDR4 DIMM, where the first and second FPGAs are operable to share access to the first and second DDR4 DIMMs and provide connectivity to a plurality of network resources. The dual-port design enables the use of existing SDRAM, MRAM and RRAM chips at low speed rates to reach DDR4 2.0 speed DIMM devices. The dual-port DDR4 DIMM comprises 1-to-2 data buffer splitters and a DDR3 or DDR2 to DDR4 bus adaptation/termination/relaying circuits to increase (e.g., double or quadruple) the chip speed of SDRAM, MRAM, and RRAM chips.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: December 26, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventor: Xiaobing Lee