Abstract: A blade server has a casing, a plurality of blade server module boards, a first chassis management controller (CMC) and a second CMC. There are a plurality of main board slots at a first side of the casing and at least a first CMC slot and a second CMC slot at a second side of the casing opposite to the first side. The plurality of main board slots are all electrically connected to both of the first CMC slot and the second CMC slot, wherein the first CMC slot and the second CMC slot are electrically connected to each other. The plurality of blade server module boards are plugged into the plurality of main board slots. The first CMC and the second CMC are redundant to each other. When one of the two CMCs malfunctions, the blade server module boards are controlled by the other one CMC functioning normally.

Abstract: A blade server has a casing, a plurality of blade server module boards, a first chassis management controller (CMC) and a second CMC. There are a plurality of main board slots at a first side of the casing and at least a first CMC slot and a second CMC slot at a second side of the casing opposite to the first side. The plurality of main board slots are all electrically connected to both of the first CMC slot and the second CMC slot, wherein the first CMC slot and the second CMC slot are electrically connected to each other. The plurality of blade server module boards are plugged into the plurality of main board slots. The first CMC and the second CMC are redundant to each other. When one of the two CMCs malfunctions, the blade server module boards are controlled by the other one CMC functioning normally.

Abstract: The voltage monitoring circuit includes a first multiplexer, a controller, a resistor-network circuit and a first comparison circuit. The first multiplexer receives a plurality of first subject voltages. The controller controls the first multiplexer to output one of the plurality of first subject voltages and generates a testing signal including a plurality of electric potentials. The controller is configured to output the plurality of electric potentials switching according to a switch command. The resistor-network circuit is configured to sequentially generate a plurality of first reference voltages according to switches of the plurality of potentials. The first comparison circuit is configured to sequentially compare each of the plurality of first reference voltages to the first subject voltage for sequentially outputting a plurality of first comparing results and sending the plurality of first comparing results to the controller so that a voltage value of the first subject voltage is determined.

Abstract: A micro server is provided. The micro server includes a plurality of computer boards, at least one switch device, and a baseboard. The plurality of computer boards are for data processing. The switch device is electrically connected to the plurality of computer boards and is for data communication between the plurality of computer boards. The baseboard is for data communication and power supply. The communication between the plurality of computer boards is through the baseboard and the plurality of computer boards communicate with the switch device and the external network by Serial Rapid I/O (SRIO).

Abstract: A server system comprises base boards connected in series. Each base board is connected to virtual media apparatus. Each virtual media apparatus includes system-on-chips, a switch unit, a control unit and a programmable module. The switch unit couples with the system-on-chips through a serial bus. The control unit couples with the switch unit to transform a serial signal to an intranet signal. The programmable module couples with the switch unit and the control unit to receive a control signal generated by the control unit and generate a selecting signal according to the control signal. The selecting signal is transferred to the switch unit to select one of the system-on-chips to be connected to the control unit.

Abstract: A micro server is provided. The micro server includes a plurality of computer boards, at least one switch device, and a baseboard. The plurality of computer boards are for data processing. The switch device is electrically connected to the plurality of computer boards and is for data communication between the plurality of computer boards. The baseboard is for data communication and power supply. The communication between the plurality of computer boards is through the baseboard and the plurality of computer boards communicate with the switch device and the external network by Serial Rapid I/O (SRIO).

Abstract: An electronic device for a micro server is provided. The electronic device includes a plurality of computer boards connected to a base board. Each of the plurality of computer boards includes a BIOS module, a first SOC, a second SOC, a logic module, a managing module, a PHY, and a first connecting interface. The BIOS module is for storing a BOIS. The first and second SOCs are for processing data. The logic module is connected to the first SOC, the second SOC, and the BIOS module respectively, and is for controlling the first SOC and the second SOC.

Abstract: The fan controller controls a plurality of fans in a server system according to a fan control signal. The fan controller comprises a control unit, a current monitor, a power supply module, current sampling units and switches. The power supply module transfers power to the fans through branch power lines respectively. The current sampling units and switches are disposed on the branch power lines respectively. The control unit switches the switches and the current sampling units sample current signals in the branch power lines respectively. When the current monitor monitors one of the current signals being over a threshold value, the current monitor issues an over-current signal to the control unit to turn off the corresponding switch to cut off the power supplied to the corresponding fan by the power supply module.

Abstract: A server system comprises a fan backplate, a server array, a substrate, a first fan controller and a second fan controller. The fan backplate couples with fans. The server array includes calculation nodes. The substrate has a multiplexer. The calculation nodes couple with the multiplexer. The first fan controller and the second fan controller couple with the calculation nodes through the multiplexer. A fan control signal is generated according to the real-time temperature of the calculation nodes to control the fans. The first fan controller and the second fan controller form a redundancy system.

Abstract: A server system comprises base boards connected in series. Each base board is connected to virtual media apparatus. Each virtual media apparatus includes system-on-chips, a switch unit, a control unit and a programmable module. The switch unit couples with the system-on-chips through a serial bus. The control unit couples with the switch unit to transform a serial signal to an intranet signal. The programmable module couples with the switch unit and the control unit to receive a control signal generated by the control unit and generate a selecting signal according to the control signal. The selecting signal is transferred to the switch unit to select one of the system-on-chips to be connected to the control unit.

Abstract: A computer system including a first processor, an error detecting circuit and a south bridge chip is provided. The first processor outputs a first catastrophic error signal. The error detecting circuit is coupled to the first processor to receive the first catastrophic error signal. When the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, the error detecting circuit outputs an internal error reset signal. When the first catastrophic error signal changes to a first level and passes a second predetermined time, the error detecting circuit outputs a machine error reset signal. Here, the second predetermined time is greater than the first predetermined time. The south bridge chip is coupled to the error detecting circuit and reboots the computer system according the internal error reset signal or the machine error reset signal.

Abstract: A computer system including a first processor, an error detecting circuit and a south bridge chip is provided. The first processor outputs a first catastrophic error signal. The error detecting circuit is coupled to the first processor to receive the first catastrophic error signal. When the first catastrophic error signal changes to a first level and is maintained for a period exceeding a first predetermined time, the error detecting circuit outputs an internal error reset signal. When the first catastrophic error signal changes to a first level and passes a second predetermined time, the error detecting circuit outputs a machine error reset signal. Here, the second predetermined time is greater than the first predetermined time. The south bridge chip is coupled to the error detecting circuit and reboots the computer system according the internal error reset signal or the machine error reset signal.

Abstract: A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.

Abstract: A structure compatible with I2C bus and system management (SM) bus is provided. The structure includes a first device having an I2C bus interface, a second device having a SM bus interface, and a timing buffering apparatus connected between the I2C bus interface and the SM bus interface. The timing buffering apparatus provides a time delay when the first device sends data to the second device so as to meet the requirement of the second device to data holding time.