Abstract: A coil device includes a first coil a first coil formed by a first wire wound in a coil shape and a second coil formed by a second wire wound in a coil shape. The first coil includes a first portion provided inside the second coil and a second portion next to the first portion and the second coil along a winding axis of the first portion. A layer number of the first portion in its radial direction is one. A layer number of the second portion in its radial direction is plural.

Abstract: The present invention provides a device for blocking plasma backflow in a process chamber to protect an air inlet structure, comprising an air inlet nozzle tightly connected to an air inlet flange. The inner cavity of the air inlet nozzle is provided with an air inlet guide body, wherein the air inlet guide body has an upper structure, a middle structure, and a lower structure, the upper, middle, and lower structures are an integrated structure, the upper, middle, and lower structures are all cylindrical, the cross-sectional diameter of the upper structure is smaller than that of the middle structure, a gas gathering area is arranged between the middle structure and the lower structure, and the middle structure and the lower structure are connected by the gas gathering area.

Abstract: A method is disclosed for forming a diffusion break structure in a fin field effect transistor, including: performing a lithography process on a substrate to form a lithography pattern of a single diffusion break structure; etching the substrate to form an etched single diffusion break structure; performing an epitaxial growth process, forming an epitaxial-layer-covered single diffusion break structure by depositing an epitaxial layer on the surface of the substrate and the bottom surface and sidewalls of the etched single diffusion break structure; etching the epitaxial layer and the substrate in the single diffusion break structure, to form a plurality of fins arranged at intervals; forming an isolation layer between the two adjacent fins, wherein the top surface of the fins is higher than the top surface of the isolation layer; and forming gates spaced apart from each other respectively at the top of the isolation layer.

Abstract: The application discloses a method for forming a fin structure in a fin field effect transistor process, which includes: performing photolithography and etching for a first time to form a first core layer pattern and a second core layer pattern, and depositing an etching mask layer; etching back the etching mask layer to form sidewalls of the first core layer pattern and sidewalls of the second core layer pattern; performing photolithography for a second time; etching the substrate for a first time to form fins and a planar active area consisting of a substrate material; removing sidewalls of a first photoresist pattern, a second photoresist pattern and the second core layer pattern, and reserving the second core layer pattern; performing photolithography for a third time; etching the substrate for a second time to form reference layer overlay mark and a fin cut area consisting of the substrate material.

Abstract: The present application provides a dynamic illumination method based on a scan exposure machine, providing a mask used for exposure and a GDS file corresponding to the mask; dividing pattern information on the mask into n areas with the same width along the direction of movement of the mask during the exposure; performing SMO computation on the pattern information in the n areas, so as to generate n SMO files corresponding to the n areas respectively; performing combinatorial optimization on the n SMO files to obtain a DSMO file; generating a driver of a light source reflector array according to the DSMO file, the illumination; and controlling a reflector array of an exposure machine by calling the driver of the light source reflector array. The DSMO method is performed in each exposure slit area, so as to improve the illumination optimization for a pattern.

Abstract: An information classification processing method of a carbonate reservoir and an information data processing terminal. The method includes: determining rock types; determining reservoir types on the basis of different rock types; and in accordance with the determined reservoir and rock types, performing porosity and permeability intersection by utilizing measured data; fitting a curve to obtain a porosity-permeability relation formula; and calculating permeability by utilizing the formula. According to the present invention, complex carbonate reservoirs in the Middle East can be classified, and porosity-permeability relations are respectively established, thereby increasing interpretation accuracy of permeability. According to the present invention, the reservoir types and the rock types can be rapidly and systematically classified, and clear porosity-permeability relations are obtained, so that interpretation of the permeability in oil reservoir exploitation is more accurate.

Abstract: A modular linear high-bay light fixture. The modular linear high-bay light fixture may include one or more light-emitting diode (LED) drivers enclosed in a driver housing; and one or more LED light strip assemblies operatively connected to the one or more LED drivers, wherein the one or more LED light strip assemblies each may include a stack assembly enclosed in a substantially waterproof configuration.

Abstract: A high-bay light-emitting diode (LED) light fixture including, a driver chamber assembly and an LED assembly. The driver chamber assembly further includes a driver chamber body that houses a driver module and/or a controller module, and a receiver portion. The LED assembly further includes an LED housing, an LED module that supports an arrangement of LEDs, and a lens.

Abstract: A high-bay light-emitting diode (LED) light fixture. The fixture may include a driver chamber assembly. The driver chamber assembly may include a driver chamber body having an upper end and a base end, wherein the driver chamber body may be substantially dome shaped; an LED driver module operationally positioned in the driver chamber body; and a receiver portion provided at about a center portion of the upper end of the driver chamber body. The fixture may include an LED assembly. The LED assembly may include an LED housing, that may include a mating portion adapted to couple with the base end of the driver chamber body; one or more LED boards housed within the LED housing; a plurality of LEDs arranged on the one or more LED boards; and a lens, wherein the lens may be adapted to cover the one or more LED boards.

Abstract: Lighting fixtures having mounting structure openings and coverings are disclosed. According to an aspect, a lighting fixture includes a housing defining space for holding an electronic component for distributing power to one or more light sources. The lighting fixture also includes a mounting structure attached to the housing and configured to at least partially enclose the space for containing the electronic component. The mounting structure defines an opening for accessing the electronic component. Further, the mounting structure is configured to attach to light source(s). The lighting fixture also includes a covering attached to the mounting structure and arranged to cover the opening when attached.

Abstract: A high-bay light-emitting diode (LED) light fixture. The fixture may include a driver chamber assembly. The driver chamber assembly may include a driver chamber body having an upper end and a base end, wherein the driver chamber body may be substantially dome shaped; an LED driver module operationally positioned in the driver chamber body; and a receiver portion provided at about a center portion of the upper end of the driver chamber body. The fixture may include an LED assembly. The LED assembly may include an LED housing, that may include a mating portion adapted to couple with the base end of the driver chamber body; one or more LED boards housed within the LED housing; a plurality of LEDs arranged on the one or more LED boards; and a lens, wherein the lens may be adapted to cover the one or more LED boards.

Abstract: Implementations of the present specification provide a method and apparatus for determining a target user group, where the method includes: determining a seed user of a to-be-recommended product based on association behavior data of a first user for the to-be-recommended product; obtaining a similar user group of the seed user based on user features of the seed user; obtaining a probability score of a second user within the similar user group based on user features of the second user, wherein the probability score indicates a probability that the second user is a target user of the to-be-recommended product; determining probability scores of multiple users, including the second user, satisfy a predetermined condition; based on the probability scores of the multiple users, determining a target user group; and generating a recommendation for the to-be-recommended product to the target user group.

Abstract: A high-bay light-emitting diode (LED) light fixture including, a driver chamber assembly and an LED assembly. The driver chamber assembly further includes a driver chamber body that houses a driver module and/or a controller module, and a receiver portion. The LED assembly further includes an LED housing, an LED module that supports an arrangement of LEDs, and a lens.

Abstract: A method of forming a patterned film on both a bottom and a top-surface of a deep trench is disclosed. The method includes the steps of: 1) providing a substrate having a deep trench formed therein; 2) growing a film over a bottom and a top-surface of the deep trench; 3) coating a photoresist in the deep trench and over the substrate and baking the photoresist to fully fill the deep trench; 4) exposing the photoresist to form a latent image that partially covers the deep trench in the photoresist; 5) silylating the photoresist with a silylation agent to transform the latent image into a silylation pattern; 6) etching the photoresist to remove a portion of the photoresist not covered by the silylation pattern; and 7) etching the film to form a patterned film on both the bottom and the top-surface of the deep trench.

Abstract: A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer.

Abstract: A method of double-sided patterning including positioning a first silicon wafer with its back side facing upwards and forming one or more deep trenches serving as alignment marks on the back side of the first silicon wafer; performing alignment with respect to the alignment marks and forming a back-side pattern on the first silicon wafer; depositing a polishing stop layer on the back side of the first silicon wafer; flipping over the first silicon wafer and bonding its back side with the front side of a second silicon wafer; polishing the front side of the first silicon wafer to expose the alignment marks from the front side; performing alignment with respect to the alignment marks and forming a front-side pattern on the first silicon wafer; removing the second silicon wafer and the polishing stop layer to obtain a double-sided patterned structure on the first silicon wafer.

Abstract: A method of forming a patterned film on both a bottom and a top-surface of a deep trench is disclosed. The method includes the steps of: 1) providing a substrate having a deep trench formed therein; 2) growing a film over a bottom and a top-surface of the deep trench; 3) coating a photoresist in the deep trench and over the substrate and baking the photoresist to fully fill the deep trench; 4) exposing the photoresist to form a latent image that partially covers the deep trench in the photoresist; 5) silylating the photoresist with a silylation agent to transform the latent image into a silylation pattern; 6) etching the photoresist to remove a portion of the photoresist not covered by the silylation pattern; and 7) etching the film to form a patterned film on both the bottom and the top-surface of the deep trench.

Abstract: A method of back-side patterning of a silicon wafer is disclosed, which includes: depositing a protective layer on a front side of a silicon wafer; forming one or more deep trenches through the protective layer and extending into the silicon wafer by a depth greater than a target thickness of the silicon wafer; flipping over the silicon wafer and bonding the front side of the silicon wafer with a carrier wafer; polishing a back side of the silicon wafer; performing alignment by using the one or more deep trench alignment marks and performing back-side patterning process on the back side of the silicon wafer; and de-bonding the silicon wafer with the carrier wafer.

Abstract: A method of manufacturing non-photosensitive polyimide passivation layer is disclosed. The method includes: spin-coating a non-photosensitive polyimide layer over a wafer and baking it; depositing a silicon dioxide thin film thereon; spin-coating a photoresist layer over the silicon dioxide thin film and baking it; exposing and developing the photoresist layer to form a photoresist pattern; etching the silicon dioxide thin film by using the photoresist pattern as a mask; removing the patterned photoresist layer; dry etching the non-photosensitive polyimide layer by using the patterned silicon dioxide thin film as a mask; removing the patterned silicon dioxide thin film; and curing to form a imidized polyimide passivation layer. The method addresses issues of the traditional non-photosensitive polyimide process, including aluminum corrosion by developer, tapered profile of non-photosensitive polyimide layer and generation of photoresist residues.

Abstract: The present invention provides systems and methods for simulating an analog and mixed-signal circuit design comprising an analog circuit segment and a transmission gate network of a digital circuit segment, where the analog circuit segment is connected to the transmission gate network using a bi-directional connect module, where the analog circuit segment contributes with its own driving force to the digital circuit segment as an equivalent to a driver, and where the digital circuit segment contributes with its own driving force to the analog circuit segment. Additionally, in some systems and methods of the current invention, the bi-directional connect module defers to the transmission gate network any resolution of digital logic values to analog voltages, and any resolution of analog voltages to digital logic values.