Abstract: A secure system configured to perform operations on data can include a plurality of N look-up-table fabric modules each operatively coupled to a respective column of M rows of data included in an input state matrix having N columns and M rows and a processor circuit operatively coupled to the plurality of N look-up-table fabric modules, the processor circuit configured to provide unencrypted data to the plurality of N look-up-table fabric modules for encryption and configured to provide encrypted data to the plurality of N look-up-table fabric modules for decryption.

Abstract: A method operating a Graphics Processing Unit (GPU) memory can be provided by accessing specified training parameters used to train a Deep Neural Network (DNN) using a GPU with a local GPU memory, the specified training parameters including at least a specified batch size of samples configured to train the DNN. A sub-batch size of the samples can be defined that is less than or equal to the specified batch size of samples in response to determining that an available size of the local GPU memory is insufficient to store all data associated with training the DNN using one batch of the samples. Instructions configured to train the DNN using the sub-batch size can be defined so that an accuracy of the DNN trained using the sub-batch size is about equal to an accuracy of the DNN trained using the specified batch size of the samples.

Abstract: A method operating a Graphics Processing Unit (GPU) memory can be provided by accessing specified training parameters used to train a Deep Neural Network (DNN) using a GPU with a local GPU memory, the specified training parameters including at least a specified batch size of samples configured to train the DNN. A sub-batch size of the samples can be defined that is less than or equal to the specified batch size of samples in response to determining that an available size of the local GPU memory is insufficient to store all data associated with training the DNN using one batch of the samples. Instructions configured to train the DNN using the sub-batch size can be defined so that an accuracy of the DNN trained using the sub-batch size is about equal to an accuracy of the DNN trained using the specified batch size of the samples.

Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: Various processor architectures for mixed signal computation exploit the unique characteristics of advanced CMOS technologies, such as fin-based, multi-gate field effect transistors, and/or emerging technologies such as tunnel field effect transistors (TFETs). The example processors disclosed herein are cellular neural network (CNN)-inspired and eliminate the need for voltage controlled current sources (VCCSs), which have previously been utilized to realize feedback and feed-forward templates in CNNs and are the dominant source of power consumption in a CNN array. The example processors replace VCCSs with comparators, which can be efficiently realized with TFETs given their high intrinsic gain. Power efficiencies are in the order of 10,000 giga-operations per second per Watt (GOPS/W), which represents an improvement of more than ten times over state-of-the-art architectures seeking to accomplish similar information processing tasks.

Abstract: An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

Abstract: Disclosed is an example method to calculate radiation dose. The method includes receiving a tissue matrix in which the tissue matrix includes a plurality of voxels. The example method also includes producing a first plurality of transport lines with a direction controller in which each transport line is indicative of a cone of irradiated energy, and calculating at least one radiation dose with at least one deposit engine substantially in parallel with producing a second plurality of transport lines with the direction controller.

Abstract: Disclosed is an example method to calculate radiation dose. The method includes receiving a tissue matrix in which the tissue matrix includes a plurality of voxels. The example method also includes producing a first plurality of transport lines with a direction controller in which each transport line is indicative of a cone of irradiated energy, and calculating at least one radiation dose with at least one deposit engine substantially in parallel with producing a second plurality of transport lines with the direction controller.

Abstract: A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respective magnetic fringe fields. The MAMI is geometrically and/or angularly configured to exhibit a magnetization ground state bias which is dependent upon which direction the applied magnetic clock field is swept. Non-majority logic gates can be made from layouts containing the SAMIs and the MAMI which contain a smaller number of components as comparable majority logic gate layouts.

Abstract: A non-majority magnetic logic gate device for use in constructing compact and power efficient logical magnetic arrays is presented. The non-majority magnetic logic gate device includes a substrate, symmetrically aligned magnetic islands (SAMIs), at least one misaligned magnetic island (MAMI), magnetic field inputs (MFIs), and at least one magnetic field output (MFO). The SAMIs and MAMI are electrically isolated from each other but are magnetically coupled to one another through their respective magnetic fringe fields. The MAMI is geometrically and/or angularly configured to exhibit a magnetization ground state bias which is dependent upon which direction the applied magnetic clock field is swept. Non-majority logic gates can be made from layouts containing the SAMIs and the MAMI which contain a smaller number of components as comparable majority logic gate layouts.