Abstract: A system and a method are disclosed for managing memory requests in a memory controller. The method includes storing a memory request in a request queue, the request queue comprising one or more request slots; determining if the memory request in the request queue is oversubscribed to a dedicated number of the request slots of a first information processor (IP); and copying the memory request from the request queue to a replay buffer comprising one or more replay slots in a case in which the memory request is oversubscribed to the first IP.

Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A system includes a communication link coupled to an encoder and a decoder. The communication link includes a set of wires. The encoder is configured to encode a first block of input data to form a first codeword and to encode a second block of the input data to form a second codeword. The encoder is configured to generate a boundary bit based on at least one bit from each of the first codeword and the second codeword, and to send encoded data via the communication link. The encoded data includes a first set of bit values of the first codeword, a second set of bit values of the second codeword, and the boundary bit, which is located between the first set of bit values and the second set of bit values. The decoder is configured to decode the encoded data to generate a representation of the input data.

Abstract: A device includes a transmitter configured to obtain a particular set of bit values to be sent via a set of wires of a communication link. The transmitter is also configured to determine, based on a transition pattern associated with the particular set of bit values, whether to send the particular set of bit values during a single transmission period or during multiple transmission periods. The transmitter is further configured to send the particular set of bit values based on the determination.

Abstract: A system and method of performing sparse accumulation in column-wise sparse general matrix-matrix multiplication (SpGEMM) algorithms. The method includes receiving a request to perform SpGEMM based on a first matrix and a second matrix. The method includes accumulating, in a hardware buffer, a hash key and an intermediate multiplication result of the first matrix and the second matrix. The method includes performing a probe search of a hardware cache to identify a match between the hash key and a partial sum associated with the first matrix and the second matrix. The method includes generating, by a hardware adder, a multiplication result based on the partial sum and the intermediate multiplication result from the accumulation waiting buffer.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: A method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.

Abstract: A processor and a method implemented by the processor to obtain computation results are described. The processor includes a unified reuse table embedded in a processor pipeline, the unified reuse table including a plurality of entries, each entry of the plurality of entries corresponding with a computation instruction or a set of computation instructions. The processor also includes a functional unit to perform a computation based on a corresponding instruction.

Abstract: Presented is a method and apparatus for solving. The method includes receiving, by a resistive memory array, a first data, the resistive memory array comprising a plurality of cells, wherein the receiving comprises setting a plurality of resistances on the plurality of cells, wherein each of the plurality of resistances are based on the first data. The method further includes receiving, by the resistive memory array, a second data, wherein the receiving comprises applying at least one of a current and a voltage based on the second data on the plurality of cells. The method still further includes determining, by the resistive memory array, an initial unknown value, the initial value based on the first data and the second data.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method may include determining a performance characteristic using relationship information that relates a bit error rate to at least one of a programming pulse width, a temperature, a history-based predictive performance parameter, a coding scheme, and a voltage level also associated with a memory. The performance characteristic is stored and used to manage a write operation associated with the memory.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.

Abstract: Systems and methods to manage memory on a spin transfer torque magnetoresistive random-access memory (STT-MRAM) are provided. A particular method of managing memory includes determining a temperature associated with the memory and determining a level of write queue utilization associated with the memory. A write operation may be performed based on the level of write queue utilization and the temperature.