Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may disconnect from a first radio access technology (RAT) service, independent of signaling from the first RAT service, after sensing that the UE has entered a coverage hole. The UE may use a connection to a second RAT service while in the coverage hole in association with disconnecting from the first RAT service. The UE may disconnect from the second RAT service, independent of signaling from the second RAT service, after sensing that the UE has exited the coverage hole and before expiration of a radio link failure (RLF) timer for the second RAT service. The UE may reconnect to the first RAT service before expiration of an RLF timer for the first RAT service. Numerous other aspects are described.

Abstract: The present disclosure provides an accelerator circuit, a semiconductor device, and a method for accelerating convolution in a convolutional neural network. The accelerator circuit includes a plurality of sub processing-element (PE) arrays, and each of the plurality of sub PE arrays includes a plurality of processing elements. The processing elements in each of the plurality of sub PE arrays implement a standard convolutional layer during a first configuration applied to the accelerator circuit, and implement a depth-wise convolutional layer during a second configuration applied to the accelerator circuit.

Abstract: A 3D memory device is provided. The 3D memory device includes a first logic base layer, a second layer, and a third layer. The first logic base layer comprises a first type DEMUX, a plurality of second type DEMUXs coupled to the first type DEMUX, a first type MUX, and a plurality of second type MUXs coupled to the first type MUX. The second layer comprises a first group of memory units. Each of the first group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs. The third layer comprises a second group of memory units. Each of the second group of memory units is respectively coupled to a corresponding DEMUX of the plurality of second type DEMUXs and a corresponding MUX of the plurality of second type MUXs.

Abstract: An artificial intelligence (AI) accelerator device may include a plurality of on-chip mini buffers that are associated with a processing element (PE) array. Each mini buffer is associated with a subset of rows or a subset of columns of the PE array. Partitioning an on-chip buffer of the AI accelerator device into the mini buffers described herein may reduce the size and complexity of the on-chip buffer. The reduced size of the on-chip buffer may reduce the wire routing complexity of the on-chip buffer, which may reduce latency and may reduce access energy for the AI accelerator device. This may increase the operating efficiency and/or may increase the performance of the AI accelerator device. Moreover, the mini buffers may increase the overall bandwidth that is available for the mini buffers to transfer data to and from the PE array.