Abstract: A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

Abstract: In some implementations, an apparatus for processing one or more signals may include an amplifier and circuitry. The circuitry may be coupled to the amplifier. The circuitry may set a first threshold indicating a first signal strength which is a positive value, and a second threshold indicating a second signal strength greater than the first threshold. The circuitry may receive a signal having a signal strength varying over time. The circuitry may enter a first state and start a timer set to a first time period. In response to the first time period ending, the circuitry may switch to a second state. In the second state, the circuitry may determine that the signal strength of the signal is greater than the second threshold, decrease a gain of the amplifier, and switch to the first state.

Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Abstract: A device may include an oscillator and a driver. The oscillator may be coupled to circuitry providing calibration of the oscillator. The oscillator may receive from the circuitry a first signal that causes the oscillator to generate a second signal having a first frequency to be used for calibration of an analog-to-digital converter (ADC). The driver may be coupled to the oscillator and the ADC. The driver may receive the second signal from the oscillator. The driver may receive a third signal indicating an amplitude to apply to the second signal. The driver may provide, to the ADC based at least on the second signal and the third signal, an output signal having the first frequency and the amplitude.

Abstract: In some implementations, the circuitry may include a circuit configured to receive a baseband signal, the baseband signal having an intermodulated non-linear distorted portion and a harmonic distorted portion. In addition, the circuitry may include a compensator coupled to the circuit, the compensator configured to generate a value to compensate for the intermodulated non-linear distorted portion without compensating for the harmonic distorted portion. The circuitry may include where the compensator is configured to output the value. The circuitry may include where the circuit is configured to adjust the baseband signal using the value. In some embodiments, the baseband signal can be baseband voltage. In some embodiments, the value can be a complex number.

Abstract: Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.

Abstract: Provided are a double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and a modulation method. The circuit includes a three-phase main inverter circuit and a three-phase double auxiliary resonant commutator circuit. An A-phase double auxiliary resonant commutator circuit, an A-phase main inverter circuit, a B-phase double auxiliary resonant commutator circuit, a B-phase main inverter circuit, a C-phase double auxiliary resonant commutator circuit and a C-phase main inverter circuit are connected in parallel in sequence and simultaneously connected with a DC power supply in parallel. The present invention can achieve the separation of the resonant current of the double auxiliary resonant commutator circuit from the load current at the moment of current commutation, thereby effectively reducing the current stress of the auxiliary switching tubes and the efficiency can be greatly increased particularly under light load condition.

Abstract: Provided are a double auxiliary resonant commutated pole three-phase soft-switching inverter circuit and a modulation method. The circuit includes a three-phase main inverter circuit and a three-phase double auxiliary resonant commutator circuit. An A-phase double auxiliary resonant commutator circuit, an A-phase main inverter circuit, a B-phase double auxiliary resonant commutator circuit, a B-phase main inverter circuit, a C-phase double auxiliary resonant commutator circuit and a C-phase main inverter circuit are connected in parallel in sequence and simultaneously connected with a DC power supply in parallel. The present invention can achieve the separation of the resonant current of the double auxiliary resonant commutator circuit from the load current at the moment of current commutation, thereby effectively reducing the current stress of the auxiliary switching tubes and the efficiency can be greatly increased particularly under light load condition.