Abstract: The present disclosure provides a coal bump control method for sectional hydraulic fracturing regions of a near vertical ultra thick coal seam. The method includes: deepening a main shaft from a mining level to a fracturing level; excavating a cross-hole from a roof rock layer of a coal seam at the fracturing level to enter a coal seam being mined, and excavating a roadway along the strike of the coal seam; and drilling hydraulic fracturing boreholes in a dedicated fracturing roadway along an inclination angle of the coal seam to the coal seam above the roadway, wherein the length of the borehole makes the borehole in communication with a goaf, and the spacing of the boreholes along the strike and the sectional spacing of the boreholes in an inclination direction are designed according to the parameters of fracturing equipments and the fracturing length.

Abstract: A device includes integer multiplier circuits, a multiplexer circuit configured to provide portions of mantissas of a set of first data elements having a floating-point data type and portions of mantissas of a set of second data elements having the floating-point data type to respective integer multiplier circuits, wherein each integer multiplier circuit is configured to multiply a respective portion of the mantissa of a first data element by a respective portion of the mantissa of a second data element to generate a partial product. The device further includes output circuits configured to generate an output data element based on the partial products generated by the integer multiplier circuits and exponents of the set of first data elements and of the set of second data elements.

Abstract: A device includes integer multiplier circuits and a multiplexer circuit provides portions of mantissas of feature elements and portions of mantissas of weight elements to respective integer multiplier circuits, wherein the feature elements and the weight elements are floating-point data types, and wherein each integer multiplier circuit multiplies a respective portion of the mantissa of a feature element by a respective portion of the mantissa of a weight element to generate a partial product. A first shift circuit shifts bits of the partial products based on exponents of the feature elements and of the weight elements, and a first integer adder circuit adds the shifted partial products to generate a sum. A composition circuit generates an output element based on the sum generated by the first integer adder circuit, the exponents of the plurality of feature elements, and the exponents of the plurality of weight elements.

Abstract: A device includes multiplication and accumulation (MAC) cells, a feature processor circuit, and a weight processor circuit. The feature processor circuit receives, from a memory input units each comprising input feature elements from different respective channels of an input tensor, generates extended feature units each comprising an input feature element from each of the input units and from a common channel of the input tensor, and provides the extended feature units to respective MAC cells. The weight processor circuit receives, from the memory, weight units each comprising weight elements from different respective channels of a kernel, generates extended weight units each comprising a weight element from each of the weight units and from a common channel of the kernel, and provides the extended weight units to respective MAC cells.