Abstract: Disclosed is a chip heat dissipating structure, a process and a semiconductor device. The structure includes at least a chip and a package layer, the package layer encapsulates the chip, an intermediate structure for buffering temperature-varying stress generated by an internal structure of the package layer and conducting internal heat is arranged in the package layer. In present disclosure, heat generated by chip silicon is transmitted to each heat conductive protrusion through the intermediate heat conductive layer, then heat dissipation is realized through heat fin. The heat fin cooperates with the bonding pad to form double-sided heat dissipation, with good heat dissipation effect, stress deformation of the heat fin does not directly extrude the chip to avoid damage. Structure of both sides of the chip is relatively symmetrical, which balances a stress effect caused by high and low temperatures. Device has strong reliability, and production cost is low.

Abstract: A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.

Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.

Abstract: A manufacturing method for a chip packaging structure, comprising: arranging a metal heat dissipation layer on a substrate comprising at least one flange on its side surface; forming a sealing pin located on an upper surface of the flange, so that the metal heat dissipation layer, the flange and the sealing pin form a cavity for accommodating an encapsulant; attaching a chip structure on an upper surface of the metal heat dissipation layer using an adhesive layer; forming the encapsulant encapsulating an upper surface of the substrate, the metal heat dissipation layer and the chip structure, the sealing pin extends to a periphery of the upper surface of the encapsulant; performing a mechanical or chemical treatment, to make electrode connecting structures on an upper layer of the chip structure exposed outside the first encapsulant; arranging a pin layer for electrically coupling to and covering the electrode connection structures.

Abstract: Disclosed a chip packaging structure and a manufacturing method thereof. The chip packaging structure comprises: a metal heat dissipation layer; a chip structure comprising a plurality of first electrical contacts on an upper surface of the chip structure; a pin layer comprising a plurality of second electrical contacts and a plurality of separate metal bumps; an encapsulant encapsulating at least one portion of the chip structure, the metal heat dissipation layer and the pin layer, wherein at least one portion of the pin layer is exposed to an upper surface of the encapsulant, and an lower surface of the metal heat dissipation layer is exposed outside the encapsulant. The metal heat dissipation layer includes a flange on the side surface for tightly combining the metal heat dissipation layer and the encapsulant.

Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.

Abstract: A stacked package structure for a chip, can include: a substrate having a first surface and a second surface opposite thereto; a first die having an active and back faces, where the active face of the first die includes pads; a first enclosure that covers the first die; an interlinkage that extends to the first enclosure to electrically couple with the pads; a first redistribution body electrically coupled to the interlinkage, and being partially exposed on a surface of the stacked package structure to provide outer pins for electrically coupling to external circuitry; a penetrating body that penetrates the first enclosure and substrate; a second die having an electrode electrically coupled to a first terminal of the penetrating body; and a second terminal of the penetrating body that is exposed on the surface of the stacked package structure to provide outer pins for electrically coupling to the external circuitry.

Abstract: In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.

Abstract: A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.

Abstract: A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.

Abstract: Disclosed a chip packaging structure and a manufacturing method thereof.

Abstract: A package structure can include: (i) a substrate having opposite first and second surfaces; (ii) a die having opposite active and back surfaces, where the die is arranged above the first surface of the substrate, the back surface of the die is adjacent to the first surface of the substrate; (iii) pads arranged on the active surface of the die; (iv) a first encapsulator configured to encapsulate the die; (v) an interconnection structure configured to electrically connect to the pads through the first encapsulator; (vi) a second encapsulator configured to encapsulate the interconnection structure; and (vii) a redistribution structure configured to electrically connect to the interconnection structure and to provide external electrical connectivity.

Abstract: A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.

Abstract: In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.

Abstract: In one embodiment, an IC package assembly for a switching regulator, can include: a power switch chip including a control electrode and a first electrode on an obverse side and a second electrode on a reverse side, where the second electrode is configured as a switching terminal of a switching regulator; a control chip including a driving electrode and a plurality of input and output electrodes on the obverse side; and a leadframe including an extension pin, a substrate, and a plurality of discrete pins, where the extension pin is formed integrally with the substrate, and where the reverse side of the power switch chip is arranged on the substrate of the leadframe by a conductive material to electrically connect the second electrode to the substrate.

Abstract: A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.

Abstract: A chip package structure can include: a lead frame having a carrier substrate and a first lead around the carrier substrate; a first conductive post arranged on the first lead and electrically coupled with the first lead; a first chip having an active face and an inactive face opposite to the active face and attached to the carrier substrate, and electrode pads on the active face are provided with a first electrical connector; a first plastic package configured to fully encapsulate the first chip, and to partly encapsulate the lead frame, where the first plastic package includes a first surface and a second surface opposite to the first surface, where the first conductive post and the first electrical connector are exposed on the first surface, and where the first lead is exposed on the second surface, and a second lead being arranged on the first surface.

Abstract: Disclosed herein are various chip packaging structures and methods of fabrication. In one embodiment, a flip chip package structure can include: (i) a pad on a chip; (ii) an isolation layer on the chip and the pad, where the isolation layer includes a through hole that exposes a portion of an upper surface of the pad; (iii) a metal layer on the pad, where the metal layer fully covers the exposed upper surface portion of the pad; and (iv) a bump on the metal layer, where side edges of the bump do not make contact with the isolation layer.

Abstract: A package assembly can include: (i) a plurality of electrical components stacked on at least two layers; (ii) a lead frame connected to the electrical components by solder interconnection; (iii) an encapsulating compound overlapping a portion of the lead frame and the electrical components to expose portions of leads of the lead frame from the encapsulating compound; and (iv) a heat sink having a first portion arranged between two of the plurality of electrical components, where the heat sink is configured to provide a common heat dissipation path for the electrical components.