Abstract: A method and an apparatus for managing and scheduling tasks in a many-core system are presented. The method improves process management efficiency in the many-core system. The method includes, when a process needs to be added to a task linked list, adding a process descriptor pointer of the process to a task descriptor entry corresponding to the process, and adding the task descriptor entry to the task linked list; if a process needs to be deleted, finding a task descriptor entry corresponding to the process, and removing the task descriptor entry from the task linked list; and when a processor core needs to run a new task, removing an available priority index register with a highest priority from a queue of the priority index register.

Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Abstract: A method and an apparatus for determining a to-be-migrated task based on cache awareness in a computing system having multiple processor cores is disclosed. In the method, the computing system determines a source processor core and a destination processor core according to a load of each processor core. Through respectively monitoring the number of cache misses of each task and the number of executed instructions of each task in the source processor core and the destination processor core, the computing system obtain an average cache miss per kilo instructions of the source processor core and an average cache miss per kilo instructions of the destination processor core. Then, the computing system determines, according to the obtained average cache miss per kilo instructions of the source processor core and the destination processor core, a task to be migrated from the source processor core to the destination processor core.

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

Abstract: A method and an apparatus for managing and scheduling tasks in a many-core system are presented. The method improves process management efficiency in the many-core system. The method includes, when a process needs to be added to a task linked list, adding a process descriptor pointer of the process to a task descriptor entry corresponding to the process, and adding the task descriptor entry to the task linked list; if a process needs to be deleted, finding a task descriptor entry corresponding to the process, and removing the task descriptor entry from the task linked list; and when a processor core needs to run a new task, removing an available priority index register with a highest priority from a queue of the priority index register.

Abstract: A real-time multi-task scheduling method and apparatus for dynamically scheduling a plurality of tasks in the computing system are disclosed. In the method, a processor of the computing system determines that laxity correction should be performed for a currently scheduled task, and then acquires a remaining execution time of the currently scheduled task according to an execution progress of the currently scheduled task and a time for which the currently scheduled task has been executed. After acquiring a laxity of the currently scheduled task according to the remaining execution time of the currently scheduled task and a deadline of the currently scheduled task, the processor determines a priority of the currently scheduled task according to the laxity of the currently scheduled task, and re-determines a priority queue according to the priority of the task. Then, the processor scheduling the plurality of tasks according to the re-determined priority queue.

Abstract: A method and an apparatus for determining a to-be-migrated task based on cache awareness in a computing system having multiple processor cores is disclosed. In the method, the computing system determines a source processor core and a destination processor core according to a load of each processor core. Through respectively monitoring the number of cache misses of each task and the number of executed instructions of each task in the source processor core and the destination processor core, the computing system obtain an average cache miss per kilo instructions of the source processor core and an average cache miss per kilo instructions of the destination processor core. Then, the computing system determines, according to the obtained average cache miss per kilo instructions of the source processor core and the destination processor core, a task to be migrated from the source processor core to the destination processor core.

Abstract: The present invention provides a method and a system for simulating multiple processors in parallel, and a scheduler. In this embodiment, the scheduler maps debug interface information of a to-be-simulated processor requiring debugging onto the scheduler during parallel simulation of multiple processors, so that the scheduler is capable of debugging, by using a master thread, the to-be-simulated processor requiring debugging via a debug interface of the to-be-simulated processor requiring debugging pointed by the debug interface information, thereby implementing debugging during parallel simulation of multiple processors.

Abstract: A method for simulating multiple processors in parallel is provided. The scheduler create one or more slave threads using a master thread, and determines a processor that is simulated by the master thread and a processor that is simulated by a slave thread, so that the scheduler is capable of using the master thread and the one or more slave threads to invoke, through a first execute interface, the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread to execute a corresponding instruction, where the first execute interface is registered with the scheduler by the determined processor that is simulated by the master thread and the determined processor that is simulated by the slave thread. Thus simulation efficiency can be increased and resource utilization can be improved.