Abstract: A method may include: hydropyrolyzing a bio feedstock in a hydropyrolysis unit to produce at least a hydropyrolysis oil; introducing at least a portion of the hydropyrolysis oil with a hydrocarbon co-feed into a fluidized catalytic cracking unit; and cracking the hydropyrolysis oil in the fluidized catalytic cracking unit to produce at least fuel range hydrocarbons.

Abstract: A control method, device, apparatus and storage medium for a supercapacitor energy storage device is provided, where the method includes: collecting life characterization parameters of the supercapacitor energy storage device and performing life evaluation to obtain a life evaluation result, inputting the life evaluation result into a constructed fuzzy rule base, and outputting a constraint condition adjustment parameter; obtaining a constraint condition according to the constraint condition adjustment parameter, and optimizing control parameters using a genetic algorithm in conjunction with an optimized objective function to obtain first control parameters; and controlling charging and discharging currents of the supercapacitor energy storage device using a droop control method according to the first control parameters.

Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Abstract: One example includes a power control system. The power control system includes an activation controller that is powered via a first power voltage generated via a first power supply and is configured to provide an enable signal. The activation controller can assert the enable signal in response to an input activation signal to control activation of a second power supply. The second power supply can generate a second power voltage in response to the enable signal being asserted. The second power voltage can be provided to regulate power associated with ancillary electronic circuitry. The system also includes a deactivation controller that is powered via the second power voltage and is configured to generate a disable signal to de-assert the enable signal in response to one of a plurality of predetermined deactivation conditions.

Abstract: A system includes a clamp network coupled between an input and an output and configured to clamp a voltage between the input and the output to a first clamp voltage based on the presence of a trigger signal and to a second clamp voltage based on the absence of the trigger signal. The second clamp voltage is greater than the first clamp voltage and the first clamp voltage is less than a breakdown voltage of the power transistor device. A detector circuit is coupled to the input and the output. A power transistor device may also be coupled between the input and the output. The detector circuit is configured to detect a pulse signal at the input or the output while the power transistor device is off and to generate the trigger signal for a time interval based on detecting the pulse signal.

Abstract: A circuit includes a charge pump to generate an output reference voltage. A first bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between first and second bootstrap nodes of a DC/DC converter. The first bootstrap refresh circuit supplies first charge current that is sourced from the first bootstrap node to the second bootstrap node based on a control signal indicating a first operating mode of the DC/DC converter. A second bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between the first and second bootstrap nodes of the DC/DC converter. The second bootstrap refresh circuit supplies second charge current from the second bootstrap node to the first bootstrap node based on the control signal indicating a second operating mode of the DC/DC converter.

Abstract: One example includes a switching power supply. The switching power supply includes a power stage, a feedback loop, and a simulated feedback error generator. The power stage provides an output signal in response to a switching signal. The feedback loop monitors the output signal and provides a feedback error signal to adjust the switching signal to regulate the output signal. The simulated feedback error generator temporarily provides a simulated feedback error signal during a transition period from the low power mode to a high power mode of the switching power supply until the feedback loop has enough time to provide the feedback error signal.

Abstract: A circuit includes a charge pump to generate an output reference voltage. A first bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between first and second bootstrap nodes of a DC/DC converter. The first bootstrap refresh circuit supplies first charge current that is sourced from the first bootstrap node to the second bootstrap node based on a control signal indicating a first operating mode of the DC/DC converter. A second bootstrap refresh circuit receives the reference voltage from the charge pump and is coupled between the first and second bootstrap nodes of the DC/DC converter. The second bootstrap refresh circuit supplies second charge current from the second bootstrap node to the first bootstrap node based on the control signal indicating a second operating mode of the DC/DC converter.

Abstract: One example includes a switching power supply. The switching power supply includes a power stage, a feedback loop, and a simulated feedback error generator. The power stage provides an output signal in response to a switching signal. The feedback loop monitors the output signal and provides a feedback error signal to adjust the switching signal to regulate the output signal. The simulated feedback error generator temporarily provides a simulated feedback error signal during a transition period from the low power mode to a high power mode of the switching power supply until the feedback loop has enough time to provide the feedback error signal.

Abstract: One example includes a power control system. The power control system includes an activation controller that is powered via a first power voltage generated via a first power supply and is configured to provide an enable signal. The activation controller can assert the enable signal in response to an input activation signal to control activation of a second power supply. The second power supply can generate a second power voltage in response to the enable signal being asserted. The second power voltage can be provided to regulate power associated with ancillary electronic circuitry. The system also includes a deactivation controller that is powered via the second power voltage and is configured to generate a disable signal to de-assert the enable signal in response to one of a plurality of predetermined deactivation conditions.

Abstract: Systems and methods for audio plug type detection excursion are described. In some embodiments, a method may include: receiving an audio plug at an audio jack; grounding a sleeve terminal of the audio jack; applying an electrical current to a second ring terminal of the audio jack; and measuring a voltage between the second ring terminal and the sleeve terminal. In other embodiments an electronic circuit may include a controller and a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution by the controller, cause the controller to: ground a sleeve terminal of an audio jack; apply an electrical current to a second ring terminal of the audio jack; and measure a voltage between the second ring terminal and the sleeve terminal.

Abstract: Systems and methods for audio plug type detection excursion are described. In some embodiments, a method may include: receiving an audio plug at an audio jack; grounding a sleeve terminal of the audio jack; applying an electrical current to a second ring terminal of the audio jack; and measuring a voltage between the second ring terminal and the sleeve terminal. In other embodiments an electronic circuit may include a controller and a memory coupled to the controller, the memory having program instructions stored thereon that, upon execution by the controller, cause the controller to: ground a sleeve terminal of an audio jack; apply an electrical current to a second ring terminal of the audio jack; and measure a voltage between the second ring terminal and the sleeve terminal.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal, wherein if the clock for the charge pump is running faster than an analog front end (“AFE”) video sampling clock, a state-machine control is configured to: skip the charge pump clock period right before a video sample signal falling edge, thereby recovering to a normal operation the next charge-pump clock period, wherein this duty cycle modulation of charge pump clock will not substantially impact charge pump output.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal.

Abstract: Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a multiplexer to commonly control the back-gates of multiple power transistors within the LDO. By doing this, the area overhead that would normally be present with these switches (of the multiplexer) can be dramatically reduced without sacrificing performance.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.

Abstract: An apparatus, comprising: a charge-pump; a sampler that samples an optical signal, including: a black sampler; a video sampler; and an analog to digital converter. The first aspect further provides a single clock that is coupled to and provides clocking signals to: a) the charge-pump logic that is coupled to the charge-pump; and b) the sampler logic that is coupled to the sampler that samples the optical signal.

Abstract: Generally, with low drop out (LDO) regulators that use multiplexed power supplies, the transistors within the regulator can use a substantial amount of area. Here, a regulator is provided that uses a multiplexer to commonly control the back-gates of multiple power transistors within the LDO. By doing this, the area overhead that would normally be present with these switches (of the multiplexer) can be dramatically reduced without sacrificing performance.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.

Abstract: An apparatus that is adapted to receive signals from an Inter-Integrated Circuit (I2C) bus is provided. The apparatus comprises a serial data (SDA) filter, a serial clock (SCL) filter, I2C interface logic, and operational circuitry. The SDA filter is adapted to receive an SDA signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SDA filter issues a disable signal when a transient in the SDA signal is detected. The SCL filter is adapted to receive an SCL signal from the I2C bus and includes a hold terminal and a disable terminal. The hold terminal of the SCL filter issues a disable signal when a transient in the SCL signal is detected. Additionally, the hold terminal of the SCL filter is coupled to the disable terminal of the SDA filter, and the hold terminal of the SDA filter is coupled to the disable terminal of the SCL filter.