Abstract: A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.

Abstract: A low-jitter random clock generation circuit includes: a clock division and pulse generation module connected to an input clock, performing frequency division processing to obtain frequency division clocks, and then detecting some frequency division clocks one by one to obtain frequency division pulses in a one-to-one correspondence; a pseudorandom number generation module connected to one frequency division clock, and generating a pseudorandom number; a status control module connected to all the frequency division clocks and the pseudorandom number to generate status control signals; and a random clock output module connected to the input clock, all the frequency division clocks, all the frequency division pulses, and all the status control signals, randomly sampling the frequency division clocks by using the frequency division pulses under control of the status control signals, and synchronously outputting the randomly sampled frequency division clocks by using the input clock, to obtain random clocks.

Abstract: In a pipelined analog-to-digital converter, at least one pipeline stage includes an N-bit sub-analog-to-digital conversion module, a first sub-digital-to-analog conversion module, a second sub-digital-to-analog conversion module, and a switched capacitor amplification module. The first sub-digital-to-analog conversion module and the second sub-digital-to-analog conversion module respectively receive and process 2N?1 digital signals, which correspondingly require 2*2N?1 switched capacitors. In a pipeline stage based on a structure of “N-bit sub-analog-to-digital conversion module+sub-digital-to-analog conversion module+subtractor+multiplier”, the non-inverting input and the inverting input of the differential input comparison are completely symmetrical, which correspondingly requires 2*2N switched capacitors.