Abstract: Provided, in an aspect, is a gene therapy vector, such as for treating retinitis pigmentosa. In an embodiment, a target specific optimization design is performed on a PROM1 gene coding sequence to obtain a nucleotide sequence particularly suitable for efficiently expressing a PROM1 protein in a mammalian cell, and a recombinant AAV virus for expressing a normal human PROM1 protein is constructed. Compared with a coding sequence which is not optimized, the expression level of the optimized PROM1 coding sequence (SEQ ID NO.:1) is increased more than three times. The sequence is particularly suitable for expression in a mammalian cell.

Abstract: A (methyl)acrolein oxidation catalyst and a preparation method therefor-in which the catalyst has a composition represented by the following formula: x(Mo12PaCsbVcDeOf)+tC/yZ in which Mo12PaCSbVcDeOf is a heteropolyacid salt main catalyst; C is a nano carbon fiber additive, and Z is a carrier thermal conduction diluent; Mo, P, Cs, V, and O represent the elements of molybdenum, phosphorus, cesium, vanadium, and oxygen, respectively; D represents at least one element selected from the group consisting of copper, iron, magnesium, manganese, antimony, zinc, tungsten, silicon, nickel, and palladium; a, b, c, e, and f represent the atomic ratio of each element, a=0.1-3, b=0.01-3, c=0.01-5, e=0.01-2, and f being the atomic ratio of oxygen required to satisfy the valence of each of the described components; x and y represent the weights of the main catalyst and the carrier thermal conduction diluent Z, and y/x=11.1-50%; and t represents the weight of the nano carbon fiber, and t/x=3-10%.

Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: Disclosed are a spherical titanium silicalite catalyst and a preparation method therefor. The spherical titanium silicalite catalyst has the following composition: xTiO2·(1?x)SiO2/yMPO4, wherein x is equal to 0.0005-0.04, y is equal to 0.005-0.20, M is a metal element selected from alkaline earth metals, transition metals or combinations of two or more thereof. The spherical titanium silicalite catalyst is prepared by the following method: (i) providing titanium silicalite raw powder with the composition of xTiO2·(1?x)SiO2, wherein x is equal to 0.0005-0.04, and y is equal to 0.005-0.20; (ii) mixing silica sol, an organic template agent and phosphate in proportion to obtain an adhesive; and (iii) mixing the adhesive with the titanium silicalite raw powder, and carrying out spray-drying molding and firing to obtain the titanium silicalite catalyst.

Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.

Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Abstract: A method for manufacturing a semiconductor device, including: acquiring a substrate, wherein a gate structure is formed on the substrate; implanting first ions into the substrate to form pre-amorphized regions at two sides of the gate structure respectively; implanting second ions into the pre-amorphized regions to form amorphized regions in the pre-amorphized regions respectively; forming first sidewalls each at a respective one of the two sides of the gate structure; performing a second doping process to form first doped regions in the amorphized regions; forming second sidewalls each at a side of a respective first sidewall; and forming a heavily-doped source region and a heavily-doped drain region in the first doped regions respectively.

Abstract: The present application is directed to display panel and display device. The display panel includes first substrate and second substrate, first signal line layer, support posts, and encapsulation glue located at one end of the non-display area away from the display area. The first signal line layer includes a first signal line located between the encapsulation glue and the display area and a second signal line located at the display area. Width of the first signal line is greater than that of the second signal line. The support posts include a main support post and an auxiliary support post. An area between the encapsulation glue and the display area is provided with main supports and auxiliary support posts. The first signal line does not overlap with the main support post and the first signal line overlaps with the auxiliary support post in a direction perpendicular to the display panel.

Abstract: In a data storage method, a storage system comprises first and second medium layers for data storage, wherein the performance of the first medium layer is different from the performance of the second medium layer. Based on the performance difference between the two layers, the storage system stores data in the first medium layer and the second medium layer based on different erasure code ratios. The different erasure code ratios correspond to different write amplification, and result in different storage space utilization.

Abstract: A method for testing a memory and a memory testing device are provided. The method for testing the memory includes writing data to a memory including a candidate storage unit, a fuse, and a redundant unit for replacing the candidate storage unit through the fuse when the candidate storage unit is determined to be defective; adjusting a temperature of the memory, and while adjusting the temperature, repeatedly refreshing the memory and recording the state of the fuse; reading the data of the memory if the temperature of the memory is stable at a predetermined temperature; and determining that the fuse is defective if the read data of the memory has an error.

Abstract: An embodiment of the present application provides a test method for tolerance against the hot carrier effect, applied to an I/O circuit of a memory, the I/O circuit having an output terminal, comprising: controlling the output terminal to alternately output a first level and a second level, the first level being higher than the second level; obtaining a degradation rate of an output performance parameter of the I/O circuit according to the first level and the second level; and obtaining tolerance of the I/O circuit against the hot carrier effect based on the degradation rate.

Abstract: The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

Abstract: A method for determining a repaired line and a repairing line in a memory includes the following: writing first preset data sets into respective lines in a normal region, and writing second preset data sets into respective lines in a redundancy region; repairing the lines in the normal region by using the lines in the redundancy region; reading data from the lines in the normal region after repairing; and determining a repaired line in the normal region and a repairing line in the redundancy region according to the data of the lines in the normal region, the data of the lines in the normal region after repairing, or the data of the lines in the redundancy region.

Abstract: The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

Abstract: A test method for an alignment error includes: providing a substrate, wherein a first conductive layer and a second conductive layer are arranged on the substrate at intervals, and the first conductive layer and the second conductive layer are arranged in a first direction; acquiring a first distance; acquiring a first resistance of the first conductive layer and a second resistance of the second conductive layer; acquiring an actual distance between the first conductive layer and the second conductive layer according to the first distance, the first resistance, and the second resistance; and acquiring a value of the alignment error between the first conductive layer and the second conductive layer based on the actual distance and a standard distance between the first conductive layer and the second conductive layer.

Abstract: A method for manufacturing a semiconductor device, including: acquiring a substrate, wherein a gate structure is formed on the substrate; implanting first ions into the substrate to form pre-amorphized regions at two sides of the gate structure respectively; implanting second ions into the pre-amorphized regions to form amorphized regions in the pre-amorphized regions respectively; forming first sidewalls each at a respective one of the two sides of the gate structure; performing a second doping process to form first doped regions in the amorphized regions; forming second sidewalls each at a side of a respective first sidewall; and forming a heavily-doped source region and a heavily-doped drain region in the first doped regions respectively.

Abstract: An illustrative example embodiment of a device for controlling movement of an elevator car includes an emergency stopping supervisor, such as a processor and memory associated with the processor. The emergency stopping supervisor is configured to: determine when an indication from an electrical protection device indicates that the elevator car should be stopped, issue a command for the elevator car to move at a reduced speed, monitor continued movement of the elevator car at the reduced speed, and continue to allow the elevator car to move at the reduced speed until a selected condition exists or immediately cause the elevator car to stop if the reduced speed is not within a predetermined range.

Abstract: An adjacent safety configuration for an elevator includes a second pair of safeties displaced from a first pair of safeties by at least 0.1 seconds of travel time at a rated speed of the elevator. An adjacent safety configuration for an elevator including a second pair of safeties displaced from the first pair of safeties to provide a predetermined time period before the second pair of safeties pass over a point on a guide rail previously passed over by the first pair of safeties to permit the guide rail surface to decrease by a predetermined temperature. A method of spacing an adjacent safety configuration for an elevator system including de-rating a pair of trailing safeties with respect to a pair of leading safeties as a function of a rated speed of the elevator and a spacing between the pair of trailing safeties and the pair of leading safeties.

Abstract: Methods for treating or preventing COPD and associated conditions in a patient are provided. Methods comprising administering to a subject in need thereof a therapeutic composition comprising an interleukin-33 (IL-33) antagonist, such as an anti-IL-33 antibody or antigen-binding fragment thereof, are provided.

Abstract: A display panel and a display device are provided. The display panel comprises a display area; a non-display area surrounding the display area; a first edge; and a first insulating layer. The non-display area includes a binding area disposed between the display area and the first edge, and the binding area includes a plurality of bonding pads. The first insulating layer includes a plurality of through-holes disposed at the binding area and one-to-one corresponding the plurality of bonding pads, and a through-hole at least partially exposes a corresponding bonding pad. The first insulating layer includes a sub-edge arranged adjacent to the first edge, and a distance between the sub-edge and the first edge is D1, and the bonding pad has a first bonding pad edge arranged adjacent to the first edge, and a distance between the first bonding pad edge and the first edge is D2, where D1?D2.