Patents by Inventor Xiao FANGYUAN

Xiao FANGYUAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor structure forming method
    Patent number: 10964540
    Abstract: The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: March 30, 2021
    Assignees: Semiconductor Manufacturing (Beijing) International Corporation, Semiconductor Manufacturing (Shanghai) International Corporation
    Inventor: Xiao Fangyuan
  • SEMICONDUCTOR STRUCTURE FORMING METHOD
    Publication number: 20200279734
    Abstract: The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as
    Type: Application
    Filed: October 22, 2019
    Publication date: September 3, 2020
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Xiao FANGYUAN