Abstract: Embodiments of the disclosure provide a circuit, chip, system, and method for eliminating random perturbation. The circuit includes a weight calculating module for receiving digital signals and random perturbation digital quantity, using least mean square error algorithm to calculate weight deviation iteration coefficient based on digital signal and digital quantity, and updating perturbation weight in real-time according to weight deviation iteration coefficient; and a perturbation eliminating module for eliminating perturbation signal in output digital signal of quantizer according to perturbation weight updated in real-time and updating perturbation weight in real-time according to weight deviation iteration coefficient, and then calculating current perturbation weight in real time to realize self-calibration of perturbation weight.

Abstract: The present application discloses a battery equalization system, a vehicle, a battery equalization method, and a storage medium. The battery equalization system includes: a collection circuit; an equalization circuit; a controller, connected to the collection circuit and the equalization circuit; and a power supply branch circuit, controlled by the controller to get connected to a power supply unit and the battery equalization system when a vehicle is in an OFF gear and a cell needs enabling of equalization, so that the power supply unit supplies power to the battery equalization system.

Abstract: The present application discloses a battery equalization system, a vehicle, a battery equalization method, and a storage medium. The battery equalization system includes: a collection circuit; an equalization circuit; a controller; a charging branch circuit, connected to a charging device and a battery pack; and a first power supply branch circuit, connected to the charging device and the battery equalization system, and configured to supply power to the battery equalization system. When a state-of-charge of the battery pack is full and a cell in the battery pack needs enabling of equalization, the controller controls the charging branch circuit to disconnect, and controls the first power supply branch circuit to keep connected, so that an equalization module performs equalization processing on the cell that needs enabling of equalization.

Abstract: A clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.

Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: A battery equalization method includes: obtaining a voltage value of a to-be-equalized cell in a battery pack; obtaining a reference voltage value required for equalization; determining a target equalization duration of the to-be-equalized cell according to a voltage value of the to-be-equalized cell, the reference voltage value, and a preset equalization duty cycle, where the equalization duty cycle is a ratio of an equalization period in a unit cycle to the unit cycle, and the unit cycle includes the equalization period and a sampling period; and controlling equalization of the to-be-equalized cell in the equalization period in the unit cycle according to the target equalization duration. According to this method, sampling is separated from equalization in a unit cycle, thereby ensuring accuracy of collected battery information, making the calculated equalization duration relatively accurate, and improving equalization effects of the battery pack.

Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.

Abstract: The present disclosure provides a differential clock cross point detection circuit and a detection method. The detection circuit includes: a first MOS transistor (M1), a second MOS transistor (M2) and a capacitor (C); a drain of the first MOS transistor (M1) is connected to a negative terminal (CLK?) of a differential clock, a gate of the first MOS transistor (M1) is connected to a positive terminal (CLK+) of the differential clock, and a source of the first MOS transistor (M1) is connected to a drain of the second MOS transistor (M2); a gate of the second MOS transistor (M2) is connected to the negative terminal (CLK?) of the differential clock, and a source of the second MOS transistor (M2) is connected to an output terminal through a node; one terminal of the capacitor (C) is connected to a node (A), and the other terminal of the capacitor (C) is grounded.

Abstract: The present disclosure provides a high-speed regenerative comparator circuit, including: a signal input stage connected with an input terminal for differential signal input; a latch for caching and serving as a differential signal output terminal; a current source connected with the signal input stage for providing a power supply voltage; a fast path connected with the output terminal and used for increasing a voltage difference of the output terminal and turning on a positive feedback network of the latch; and a reset switch, including a first reset switch and a second reset switch. In the high-speed regenerative comparator circuit of the present disclosure, the transmission delay of the regenerative comparator circuit can be greatly reduced; and in a latch phase, a bias voltage is disconnected by means of timing control, and thus the power consumption of a comparator can be reduced. The present disclosure has simple circuit and high reliability.

Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

Abstract: The present disclosure provides a one-time programmable capacitive fuse bit, including an upper plate, the upper plate includes a plurality of fuses arranged side by side and spaced by an internal from each other, middle portions of two adjacent fuses are connected to each other; a connecting portion connected to the fuse is disposed above two ends and the middle portion of each of the plurality of fuses; the fuse bit further includes a lower plate corresponding to the two ends and the middle portion of the fuse, the lower plate is disposed below the fuse; the lower plate corresponding to the middle portion of the fuse is opposite to the connecting portion corresponding to the middle portion of the fuse; a hollow portion is disposed between the lower plate corresponding to the middle portion of the fuse and the lower plate corresponding to both ends of the fuse.

Abstract: A duty cycle adjustment apparatus comprises a first edge extraction unit for extracting a rising edge of a first clock signal; a locking discrimination unit configured to output a control signal according to a comparison result between a discrimination voltage and a stabilized voltage, and select to connect the first clock signal or the clock output signal; an integration unit, configured to convert the feedback signal into the stabilized voltage, amplify the stabilized voltage to reach a reference voltage, and output a control voltage; a charge pump, configured to output a second clock signal according to the control voltage; a second edge extraction unit, configured to extract a falling edge of the second clock signal; and a phase discriminator, configured to compare a phase of the rising edge of the first clock signal with a phase of the falling edge of the second clock signal to generate the clock output signal.

Abstract: The present disclosure provides a circuit for generating a multi-phase clock having random disturbance added thereto. The circuit for generating a clock includes a main clock module, a random signal generation module and a buffer matrix switch module. The main clock module generates N multi-phase clock signals; and the buffer matrix switch module randomly switches, under the control of a random control signal output by the random signal generation module, transmission paths of the input N multi-phase clock signals, and outputs N multi-phase clock signals with random disturbance. In the present disclosure, the clock phase error is whitened by adding random disturbance. Only with a small loss of signal-to-noise ratio, the influence of a multi-phase clock phase error on the performance of a high-precision TI ADC can be eliminated in real time, and the influence of the fluctuation of a clock phase error can be tracked and eliminated.

Abstract: The present disclosure provides a clock driver circuit, including: an input stage, a double-ended to single-ended conversion stage and a driver output stage connected in sequence. The input stage includes two mutually loaded differential amplifiers and a common mode negative feedback loop. The differential amplifiers are connected to a differential clock signal for amplification to generate a common mode voltage. The common mode feedback circuit is connected to an output end of the differential amplifiers to stabilize the output amplitude of the common mode voltage. The double-ended to single-ended conversion stage converts a differential sine clock signal output by the double-ended common mode voltage into a single-ended square wave clock signal. The driver output stage includes a multi-stage cascaded push-pull phase inverter to improve the drive capability of the square wave clock signal.

Abstract: A control method includes the following steps: when the DC-DC converter works every time, acquiring total time TC for controlling an H-bridge in a third mode and total time TD for controlling the H-bridge in a fourth mode, and acquiring set time Ti for controlling the H-bridge in the third mode and set time Tm for controlling the H-bridge in the fourth mode in each working cycle during a working process of the DC-DC converter; judging a relation between the TC and the TD; and selecting the mode for controlling the H-bridge when the DC-DC converter is started according to the relation between the total time TC and the total time TD, and alternately controlling the H-bridge according to the Ti and the Tm, the second switch transistor, the third switch transistor and the fourth switch transistor in the H-bridge to be relatively balanced.

Abstract: The present application discloses a battery equalization system, a vehicle, a battery equalization method, and a storage medium. The battery equalization system includes: a collection circuit; an equalization circuit; a controller; a charging branch circuit, connected to a charging device and a battery pack; and a first power supply branch circuit, connected to the charging device and the battery equalization system, and configured to supply power to the battery equalization system. When a state-of-charge of the battery pack is full and a cell in the battery pack needs enabling of equalization, the controller controls the charging branch circuit to disconnect, and controls the first power supply branch circuit to keep connected, so that an equalization module performs equalization processing on the cell that needs enabling of equalization.

Abstract: A battery equalization method includes: obtaining a voltage value of a to-be-equalized cell in a battery pack; obtaining a reference voltage value required for equalization; determining a target equalization duration of the to-be-equalized cell according to a voltage value of the to-be-equalized cell, the reference voltage value, and a preset equalization duty cycle, where the equalization duty cycle is a ratio of an equalization period in a unit cycle to the unit cycle, and the unit cycle includes the equalization period and a sampling period; and controlling equalization of the to-be-equalized cell in the equalization period in the unit cycle according to the target equalization duration. According to this method, sampling is separated from equalization in a unit cycle, thereby ensuring accuracy of collected battery information, making the calculated equalization duration relatively accurate, and improving equalization effects of the battery pack.

Abstract: The present application discloses a battery equalization system, a vehicle, a battery equalization method, and a storage medium. The battery equalization system includes: a collection circuit; an equalization circuit; a controller, connected to the collection circuit and the equalization circuit; and a power supply branch circuit, controlled by the controller to get connected to a power supply unit and the battery equalization system when a vehicle is in an OFF gear and a cell needs enabling of equalization, so that the power supply unit supplies power to the battery equalization system.