Patents by Inventor Xiaogang Qiu

Xiaogang Qiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7188324
    Abstract: A method and apparatus provides a mechanism to transform or “morph” Formal verification method assertions so that an assertion defined in one Design Under Test (DUT) can be replicated, or derived, to propagate into other related DUTs. Using the method and apparatus of the present invention, individual DUTs can better leverage assertions defined independently in other DUT environments. This, in turn, provides for greater productivity and a faster, smoother verification process-using Formal and Assertion Based Verification methods.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: March 6, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Xiaogang Qiu, Si-En Chang
  • Publication number: 20060277363
    Abstract: Embodiments of the present invention facilitate implementing external storage systems using commodity computer components to achieve high performance and reliability. An exemplary method facilitates dynamic repairing of disk failures for RAID1 storage coherently across a plurality of loosely coupled storage controller computers via message communications through network interfaces. An exemplary method facilitates snapshot function coherently across a plurality of loosely coupled storage controller nodes via message communications through network interfaces. An exemplary method facilitates to detect, tolerate, and repair temporary target device failures in a networked storage system. An exemplary target device may contain a plurality of disk devices, and a temporary target device failure may due to many reasons such as a network or software glitch.
    Type: Application
    Filed: May 22, 2006
    Publication date: December 7, 2006
    Inventors: Xiaogang Qiu, Ningchuan Shen
  • Publication number: 20040194094
    Abstract: One embodiment of the present invention facilitates favoring the performance of a single-threaded application in a computer system that supports simultaneous multi-threading (SMT), wherein multiple threads of execution simultaneously execute in an interleaved manner on functional units within a processor. During operation, the system maintains a priority for each simultaneously executing thread. The system uses these priorities in allocating a shared computational resource between the simultaneously executing threads, so that a thread with a higher priority is given preferential access to the shared computational resource. This asymmetric treatment of the threads enables+ the system to favor the performance of a single-threaded application while performing simultaneous multi-threading.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Inventors: Xiaogang Qiu, Si-En Chang