Abstract: A data storage apparatus comprising a plurality of data storage devices configured to store data blocks, and one or more protection devices configured to store protection blocks, wherein the data devices and the protection devices are associated by a plurality of stripes, wherein each stripe comprises a memory block on each data device or protection device, and wherein each protection block in a protection device comprises a value for reconstructing storage blocks in the same stripe, and a controller configured to select a data device, store data blocks sequentially to the memory blocks in the selected data devices, store protection blocks in the protection devices for each updated stripe, read data blocks from a selected data device, and reconstruct damaged storage devices. It operates a cold storage system with less power consumption, low component wear, and flexible in capacity expansion.

Abstract: A cold storage system includes data storage devices configured to store data blocks and parity storage devices configured to store protection blocks. The data storage devices and the parity storage devices form a multiple dimensional matrix having multiple rows and multiple columns. A controller receives a data write request to write a plurality of data blocks to the system. The controller selects a data storage device for storing the plurality of data blocks, and writes the data blocks sequentially into memory blocks of the selected data storage device, each data block belonging to a row stripe distributed over one row of the matrix and to a column stripe distributed over one column of the matrix. After the controller generates a row protection block for the row stripe and a column protection block for the column stripe, the controller writes the row protection block to a parity storage device in the row, and the column protection block to a parity storage device in the column.

Abstract: The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.

Abstract: A window cleaning robot (100), a window cleaning robot system and a method for controlling the window cleaning robot are disclosed. The window cleaning robot (100) comprises a window cleaning robot body (10), a detecting module disposed on the window cleaning robot body (10) and configured to detect an environment outside the window cleaning robot body (10), and a controlling device connected to the detecting module and configured to control an action of the window cleaning robot body (10) based on a data detected by the detecting module.

Abstract: The present disclosure provides a cleaning robot system, a cleaning robot and a method for controlling a cleaning robot. The cleaning robot system includes a cleaning robot and a control terminal. The cleaning robot includes a camera set and a WIFI communication component, the camera set is configured to shoot images around the cleaning robot so as to generate panoramic image information, and the WIFI communication component is configured to generate a wireless communication between the cleaning robot and the control terminal so as to send the panoramic image information to the control terminal. The control terminal is configured to perform wireless communication with the WIFI communication component so as to receive the panoramic image information, and to generate a control instruction according to the panoramic image information for controlling the cleaning robot.

Abstract: A data storage apparatus comprising a plurality of data storage devices configured to store data blocks, and one or more protection devices configured to store protection blocks, wherein the data devices and the protection devices are associated by a plurality of stripes, wherein each stripe comprises a memory block on each data device or protection device, and wherein each protection block in a protection device comprises a value for reconstructing storage blocks in the same stripe, and a controller configured to select a data device, store data blocks sequentially to the memory blocks in the selected data devices, store protection blocks in the protection devices for each updated stripe, read data blocks from a selected data device, and reconstruct damaged storage devices. It operates a cold storage system with less power consumption, low component wear, and flexible in capacity expansion.

Abstract: The present disclosure provides a window-cleaning robot and a method for controlling the same. The robot includes: a body; a vacuum suction port disposed on the body; a suction detector configured to detect a vacuum suction value generated at the vacuum suction port; a light-emitting assembly disposed on the body, a light-emitting area of the light-emitting assembly being configured corresponding to the vacuum suction value; and a controller, connected with the suction detector and the light-emitting assembly respectively and configured to light all or a part of light-emitting area of the light-emitting assembly according to the vacuum suction value, for reminding the user.

Abstract: System and method for supporting multiple vSwitches on a single host server. In one aspect, embodiments according to the present disclosure include a system and method for supporting multiple vSwitches on a single host server. In one aspect, a set of packet processor threads are instantiated to process data packets on behalf of all vSwitches deployed on the host server. For a data packet received at a port of the host server, a packet processor determines the datapath based on a mapping table and processes the packet according to the rules defined for that datapath. In one aspect, ports (physical and/or virtual) are able to be configured to specified vSwitches dynamically.

Abstract: A system on a chip includes a network, an interface and a bridge module. The network includes one or more devices. The network is configured to operate in a first domain. Communication in the first domain is based on a first set of read and write ordering rules. An interface is connected between the network and a second chip. Communication between the interface and the second chip is in a second domain. Communication in the second domain is based on a second set of read and write ordering rules. The second set of read and write ordering rules are different than the first set of read and write ordering rules. The bridge module is configured to map communication transactions between the first domain and the second domain.

Abstract: System and method for supporting multiple vSwitches on a single host server. In one aspect, embodiments according to the present disclosure include a system and method for supporting multiple vSwitches on a single host server. In one aspect, a set of packet processor threads are instantiated to process data packets on behalf of all vSwitches deployed on the host server. For a data packet received at a port of the host server, a packet processor determines the datapath based on a mapping table and processes the packet according to the rules defined for that datapath. In one aspect, ports (physical and/or virtual) are able to be configured to specified vSwitches dynamically.

Abstract: The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.

Abstract: A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided.

Abstract: Aspects of the invention may be found in a method and system for testing an integrated circuit and may comprise an address selector, data selector and staging register coupled to a signal generator. The address selector may comprise a direct access memory test (DAMT) mode address control input and one or more output address pins coupled to an embedded memory device under test (DUT). The data selector may be coupled to at least one data pin and control pin of the signal generator and may comprise a DAMT mode data control input and at least one data output coupled to embedded memory DUT. A staging register comprising a first output clock rate which is one-quarter (¼) its input clock rate and matches a DUT burst write frequency may be coupled to an input of the data selector. A DAMT mode control may configure the memory DUT for DAMT operation.

Abstract: A system for the accelerated re-provisioning of data over cable service interface specification (DOCSIS) configuration files between a DOCSIS provisioning server and a plurality of network nodes that are configured according to the DOCSIS configuration files is provided.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without initiation by a central processing unit (CPU). The resetting may occur via a virtual CPU. The CPU and the virtual CPU may be integrated on a single chip. The signal generation and EEPROM resetting may occur via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.

Abstract: Methods and systems for hardware controlling of an electrically erasable programmable read only memory (EEPROM) are described herein. Aspects of the invention may include generating a clock signal at a frequency suitable for EEPROM operation and resetting an EEPROM utilizing the generated clock signal and a hardware generated data signal without intervention from a central processing unit (CPU). The resetting may occur via a virtual CPU. Another aspect of the invention may have the signal generation and EEPROM resetting occurring via a virtual CPU integrated within a finite state machine. A frequency counter may be utilized to generate a clock signal from a clock source having a higher frequency than that required by the EEPROM.

Abstract: A method, apparatus, and gateway allows a variety of client devices to access information from current information providers, and the information is adapted to accommodate the differing formats of the client devices. Speech processing, text-to-speech (TTS), speech feature transmission on heterogeneous networks, quality of service (QoS) support for real-time applications, transcoding, transformation, publish rendering, multimedia contents analysis, and speech coding may be supported.

Abstract: Methods for identifying devices may include receiving by one or more memory devices, one or more of a plurality of read memory device ID commands. The one or more memory devices may respond to the received one or more of the plurality of read memory device ID commands. The response may include identification information corresponding to the one or more memory devices. The one or more of a plurality of read memory device ID commands may correspond to one or more of a plurality of supported memory devices. At least one access protocol may be utilizing for performing reading, erasing, and/or writing to the one or more memory devices, if the response identifies the one or more memory devices as one of the one or more of the plurality of supported memory devices.