Patents by Inventor Xiaogen YIN

Xiaogen YIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021483
    Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 18, 2024
    Inventors: Huilong ZHU, Yongkui ZHANG, Xiaogen YIN, Chen LI, Yongbo LIU, Kunpeng JIA
  • Patent number: 11827988
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: November 28, 2023
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xiaogen Yin, Chen Li, Anyan Du, Yongkui Zhang
  • Publication number: 20220389591
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Application
    Filed: August 18, 2022
    Publication date: December 8, 2022
    Inventors: Huilong ZHU, Xiaogen YIN, Chen LI, Anyan DU, Yongkui ZHANG
  • Patent number: 11447876
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: September 20, 2022
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Xiaogen Yin, Chen Li, Anyan Du, Yongkui Zhang
  • Publication number: 20210222303
    Abstract: An embodiment of the present disclosure provides an etching method, having the following steps: forming a modified layer having a thickness of one or several atom layers on a selected region of a surface of a semiconductor material layer by using a modifier; and removing the modified layer. When a semiconductor is processed, this method achieves precise control over the etching thickness and improves the etching rate at the same time.
    Type: Application
    Filed: September 21, 2018
    Publication date: July 22, 2021
    Inventors: Huilong ZHU, Xiaogen YIN, Chen LI, Anyan DU, Yongkui ZHANG
  • Publication number: 20210193533
    Abstract: The disclosed technology provides a semiconductor device, a manufacturing method thereof, and an electronic device including the device. An example semiconductor device includes a substrate; a first device and a second device on the substrate. Each of the first device and the second device include a first source/drain layer, a channel layer, and a second source layer that are sequentially stacked, from bottom to top, on the substrate, and a gate stack around at least a part of an outer periphery of the channel layer, with sidewalls of the respective channel layers of the first device and the second device extending at least partially along different crystal planes or crystal plane families.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 24, 2021
    Inventors: Huilong ZHU, Yongkui ZHANG, Xiaogen YIN, Chen Li, Yongbo LIU, Kunpeng JIA
  • Patent number: 10796866
    Abstract: A direct current circuit breaker, including: n in number circuit breaker modules connected in series, one energy-absorbing and voltage-limiting module connected in parallel to the n in number circuit breaker modules, and a trigger module. The n in number circuit breaker modules each includes a mechanical switch and a commutation branch circuit which are connected in parallel; each commutation branch circuit includes a charging commutation module and a commutation capacitor which are connected in series; the charging commutation module is configured to charge up the commutation capacitor and produce reverse current to cut off the mechanical switch; the one energy-absorbing and voltage-limiting module is configured to absorb energy stored in inductive elements of power systems after a fault current is cut off, so as to limit voltage and protect the mechanical switch, and n is a positive integer greater than or equal to 1.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 6, 2020
    Assignee: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Zhao Yuan, Junjia He, Yuan Pan, Hui Xu, Wenting Zhao, Xiaogen Yin
  • Publication number: 20180005783
    Abstract: A direct current circuit breaker, including: n in number circuit breaker modules connected in series, one energy-absorbing and voltage-limiting module connected in parallel to the n in number circuit breaker modules, and a trigger module. The n in number circuit breaker modules each includes a mechanical switch and a commutation branch circuit which are connected in parallel; each commutation branch circuit includes a charging commutation module and a commutation capacitor which are connected in series; the charging commutation module is configured to charge up the commutation capacitor and produce reverse current to cut off the mechanical switch; the one energy-absorbing and voltage-limiting module is configured to absorb energy stored in inductive elements of power systems after a fault current is cut off, so as to limit voltage and protect the mechanical switch, and n is a positive integer greater than or equal to 1.
    Type: Application
    Filed: September 13, 2017
    Publication date: January 4, 2018
    Inventors: Zhao YUAN, Junjia HE, Yuan PAN, Hui XU, Wenting ZHAO, Xiaogen YIN