Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

Abstract: A method and an apparatus for adjusting an instruction pipeline, a memory and a storage medium. The method for adjusting the instruction pipeline includes: receiving a move-type instruction, wherein the move-type instruction includes a target operand and a first source operand, and indicates to move a data of a source address indicated by the first source operand to a target address indicated by the target operand; receiving an object instruction located after the move-type instruction in an instruction sequence, wherein the object instruction includes an object source operand, indicating that an object operation is performed with a source address indicated by the object source operand; and replacing the object source operand in the object instruction with the first source operand of the move-type instruction to obtain a modified instruction, in response to the target operand of the move-type instruction being identify to the object source operand of the object instruction.

Abstract: The present application provides a processor and a method for memory access instruction, and an electronic device, and relates to the field of computer technology. The method includes: the memory access unit generates the target physical memory address corresponding to the memory access instruction in case of receiving the memory access instruction, and transmits the target physical memory address to the cache unit and the programmable physical memory property detection unit respectively in the current clock cycle; the programmable physical memory property detection unit determines the detection result for the cache property of the target physical memory address in the current clock cycle; the cache unit performs the memory access operation at the target physical memory address based on the detection result for the cache property in the next clock cycle subsequent to the current clock cycle. This may reduce the logical depth of the critical memory access paths and improve the clock speed of the processor.

Abstract: A method and an apparatus for adjusting an instruction pipeline, a memory and a storage medium. The method for adjusting the instruction pipeline includes: receiving a move-type instruction, wherein the move-type instruction includes a target operand and a first source operand, and indicates to move a data of a source address indicated by the first source operand to a target address indicated by the target operand; receiving an object instruction located after the move-type instruction in an instruction sequence, wherein the object instruction includes an object source operand, indicating that an object operation is performed with a source address indicated by the object source operand; and replacing the object source operand in the object instruction with the first source operand of the move-type instruction to obtain a modified instruction, in response to the target operand of the move-type instruction being identify to the object source operand of the object instruction.

Abstract: Provided is a novel chemical modification method for small interfering RNA (siRNA). The method is combined with at least two of the three methods of isonucleoside modification, terminal peptide conjugation and cationic liposomes.