Abstract: A shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

Abstract: A pixel driving circuit may include a first switch circuit, a second switch circuit, a first initialization circuit, a drive circuit, a second initialization circuit, a compensation circuit, an isolation circuit, and an energy storage circuit.

Abstract: A shift register includes an output sub-circuit and a coupling sub-circuit. The output sub-circuit is coupled to a second clock signal terminal, a pull-up node and a signal output terminal. The output sub-circuit is configured to output a second clock signal received at the second clock signal terminal to the signal output terminal under a control of a voltage of the pull-up node. The coupling sub-circuit is coupled to the second clock signal terminal and a pull-down node. The coupling sub-circuit is configured to couple a voltage of the pull-down node through the second clock signal received at the second clock signal terminal.

Abstract: A shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

Abstract: A pixel driving circuit may include a first switch circuit, a second switch circuit, a first initialization circuit, a drive circuit, a second initialization circuit, a compensation circuit, an isolation circuit, and an energy storage circuit.

Abstract: A shift register unit and a driving method, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

Abstract: A shift register unit includes: an input terminal, a first voltage terminal, a second voltage terminal, a first clock terminal, a second clock terminal and an output terminal, as well as an input circuit, a control circuit and an output circuit. In addition, a method for driving the shift register unit, a gate driver composed of the shift register units, a display panel comprising the gate driver and a display device comprising the display panel are also disclosed.

Abstract: A shift register unit and a driving method, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.

Abstract: A shift register unit includes: an input terminal, a first voltage terminal, a second voltage terminal, a first clock terminal, a second clock terminal and an output terminal, as well as an input circuit, a control circuit and an output circuit. In addition, a method for driving the shift register unit, a gate driver composed of the shift register units, a display panel comprising the gate driver and a display device comprising the display panel are also disclosed.

Abstract: A shift register includes: a first control and output circuit coupled to precharge signal input terminal, first and second power supply terminals, first to third clock signal terminals, first signal output terminal, and configured to write second clock signal provided through the second clock signal terminal to the first signal output terminal during precharge and output phases, and write second operating voltage provided through the second power supply terminal to the first signal output terminal during reset phase; and a second control and output circuit coupled to the first and second power supply terminals, the third clock signal terminal, the precharge signal input terminal, second signal output terminal, and configured to write first operating voltage provided through the first power supply terminal to the second signal output terminal during the precharge and output phases, and write the second operating voltage to the second signal output terminal in the reset phase.

Abstract: A shift register includes: a first control and output circuit coupled to precharge signal input terminal, first and second power supply terminals, first to third clock signal terminals, first signal output terminal, and configured to write second clock signal provided through the second clock signal terminal to the first signal output terminal during precharge and output phases, and write second operating voltage provided through the second power supply terminal to the first signal output terminal during reset phase; and a second control and output circuit coupled to the first and second power supply terminals, the third clock signal terminal, the precharge signal input terminal, second signal output terminal, and configured to write first operating voltage provided through the first power supply terminal to the second signal output terminal during the precharge and output phases, and write the second operating voltage to the second signal output terminal in the reset phase.