Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.

Abstract: The present disclosure, in various aspects, describes technologies and techniques for use by a data storage device that includes a controller of a non-volatile memory (NVM). In one example, the controller applies a default storage format to a storage region of the NVM, the default storage format configuring the storage region as a number of distinct storage regions logically arranged along a horizontal dimension and a vertical dimension. The controller modifies the default storage format using a combination of horizontal dimension scaling and vertical dimension scaling based on a performance capability of the storage region to obtain a modified storage format. The controller applies the modified storage format to the storage region.

Abstract: Aspects of the disclosure provide systems and methods for adaptive data retention management in non-volatile memory. A solid state device (SSD) includes non-volatile memory (NVM) for storing data. The SSD is configured to determine a temperature of the NVM. If the temperature of the NVM is below a predetermined temperature, the SSD maintains a data retention refresh rate of the data stored in the NVM. If the temperature of the NVM is equal to or above the predetermined temperature, the SSD adjusts the data retention refresh rate at a first rate and then a second rate, each adjustment based on the temperature of the NVM. The first rate and the second rate are different, for example, the second rate is less than the first rate.

Abstract: Exemplary methods and apparatus are provided for read recovery in solid state devices (SSDs) with non-volatile memories (NVMs). In some examples, a dynamic priority read retry table (PRT) is generated for use with a static read retry table (RRT). In one aspect, a most recent successful read retry entry is determined from among the entries in the RRT. The most recent successful read retry entry is inserted as a first priority read retry entry within the PRT. A subsequent read recovery operation is performed using the first priority read retry entry of the PRT. In some examples, one or more neighboring values are selected for each entry in the PRT starting with the newest entry and proceeding chronologically to the oldest entry. The use of the PRT may help address die-to-die variations, block-to-block variations, or the transient changes that may occur in device physics within NVMs.

Abstract: Exemplary methods and apparatus are provided to reduce read retry latency within solid state devices (SSDs) with non-volatile memories (NVMs). The reduction in read retry latency may be accomplished in some examples by prioritizing read recovery of a regular codeword over an irregular codeword for a cross-die logical page, irrespective of the location in the page with read errors. In an illustrative example, a processor (a) performs a read retry for a second codeword by setting a read voltage level to a first level for a first die, then advancing through a read retry table for the second die until the second codeword is read successfully, and (b) then performs a read retry for the first codeword by setting a read voltage level for the second die to a second level, then advancing through a read retry table for the first die until the first codeword is successfully read.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Aspects of the disclosure provide systems and methods for adaptive data retention management in non-volatile memory. A solid state device (SSD) includes non-volatile memory (NVM) for storing data. The SSD is configured to determine a temperature of the NVM. If the temperature of the NVM is below a predetermined temperature, the SSD maintains a data retention refresh rate of the data stored in the NVM. If the temperature of the NVM is equal to or above the predetermined temperature, the SSD adjusts the data retention refresh rate at a first rate and then a second rate, each adjustment based on the temperature of the NVM. The first rate and the second rate are different, for example, the second rate is less than the first rate.

Abstract: A storage device with a memory may optimize the setting of a read threshold or read level. A feedback mechanism may be used responsive to there being a read retry error for providing the read threshold from the read retry. Specifically, recovery from a read failure can provide feedback information for dynamically optimizing read threshold values. Read threshold adjustments may occur each time there is a successful error recovery. The read threshold adjustment scheme may select one logical page or multiple logical pages from a recovered region. If a read threshold is found to be working, this threshold may be part of a feedback message to make an informed adjustment that optimizes the read threshold of other pages.

Abstract: Methods and systems for decoding raw data may select a preliminary read-level voltage from a sequence of read-level voltages based on a decoding success indicator and execute a preliminary hard decoding operation to decode raw data read from a plurality of memory cells using the preliminary read-level voltage. If the preliminary hard decoding operation is successful, the decoded data from the hard decoding operation is returned. If the preliminary hard decoding operation is unsuccessful, a multi-stage decoding operation may be executed to decode raw data read from the plurality of memory cells using the sequence of read-level voltages, and returning decoded data from the multi-stage decoding operation upon completion of the multi-stage decoding operation. The decoding success indicator is maintained based on results of the preliminary hard decoding operation or the multi-stage decoding operation.

Abstract: Exemplary methods and apparatus are provided for read recovery in solid state devices (SSDs) with non-volatile memories (NVMs). In some examples, a dynamic priority read retry table (PRT) is generated for use with a static read retry table (RRT). In one aspect, a most recent successful read retry entry is determined from among the entries in the RRT. The most recent successful read retry entry is inserted as a first priority read retry entry within the PRT. A subsequent read recovery operation is performed using the first priority read retry entry of the PRT. In some examples, one or more neighboring values are selected for each entry in the PRT starting with the newest entry and proceeding chronologically to the oldest entry. The use of the PRT may help address die-to-die variations, block-to-block variations, or the transient changes that may occur in device physics within NVMs.

Abstract: Exemplary methods and apparatus are provided to reduce read retry latency within solid state devices (SSDs) with non-volatile memories (NVMs). The reduction in read retry latency may be accomplished in some examples by prioritizing read recovery of a regular codeword over an irregular codeword for a cross-die logical page, irrespective of the location in the page with read errors. In an illustrative example, a processor (a) performs a read retry for a second codeword by setting a read voltage level to a first level for a first die, then advancing through a read retry table for the second die until the second codeword is read successfully, and (b) then performs a read retry for the first codeword by setting a read voltage level for the second die to a second level, then advancing through a read retry table for the first die until the first codeword is successfully read.

Abstract: A storage device with a memory may optimize the setting of a read threshold or read level. A feedback mechanism may be used responsive to there being a read retry error for providing the read threshold from the read retry. Specifically, recovery from a read failure can provide feedback information for dynamically optimizing read threshold values. Read threshold adjustments may occur each time there is a successful error recovery. The read threshold adjustment scheme may select one logical page or multiple logical pages from a recovered region. If a read threshold is found to be working, this threshold may be part of a feedback message to make an informed adjustment that optimizes the read threshold of other pages.

Abstract: Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset.

Abstract: Systems, methods, and/or devices are used to improve decoding of data read from a storage device with one or more memory devices. In one aspect, the method includes obtaining, in response to a read request, a codeword with two or more codeword portions from distinct memory portions of the storage device. When a decoding iteration on the codeword fails to satisfy predetermined decoding criteria, the method includes, for the two or more codeword portions of the codeword: determining a bit-flip count between raw read data for a respective codeword portion and a decoding result for the respective codeword portion after the decoding iteration; determining a soft information offset for the respective codeword portion based on the bit-flip count for the respective codeword portion relative to bit-flips counts for other codeword portions; and adjusting soft information for the respective codeword portion based on the soft information offset.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length to enable soft information decoding systems that use less power and/or less memory. In some implementations, the bit-tuple of a predefined length is produced using M single-bit buffer locations, where M corresponds to the predefined length of the bit-tuple. Some implementations utilize a collection of characterization vectors that include soft information values associated with the possible permutations of the bit-tuples. In turn, a sequence of bit-tuples is converted into a sequence of soft information values by retrieving a particular characterization vector, and selecting a respective soft information value from that characterization vector for each bit-tuple in the sequence.

Abstract: The various implementations described herein include systems, methods and/or devices that may enhance performance of error control encoding. The method includes receiving information data and generating parity information based on an m×k parity matrix comprising an array of b×b circulant sub-matrices, including m columns of said sub-matrices, each column comprising k said sub-matrices. The method further includes dividing the information data into a plurality of b-sized trunks and generating m parity segments. Each parity segment consists of b bits, and each parity segment is generated by multiplying each of the k b×b circulant sub-matrices in a respective column of the parity matrix by a corresponding trunk of information data, where each multiplication of a b×b circulant sub-matrix by a corresponding trunk comprises b2 concurrent computations. The method further includes generating a codeword based on the information data and the m parity segments.