Patents by Inventor Xiaohong CHENG

Xiaohong CHENG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220361954
    Abstract: Novel tools and techniques are provided for implementing intelligent assistance (“IA”) or extended intelligence (“EI”) ecosystem to placement procedures for cardiac implantable electronic device (“CIED”). In various embodiments, a computing system might analyze received one or more first layer input data (i.e., room content-based data) and received one or more second layer input data (i.e., patient and/or tool-based data), and might generate one or more recommendations for guiding a medical professional in performing a CIED placement procedure in a heart of the patient, based at least in part on the analysis, the generated one or more recommendations comprising 3D or 4D mapped guides toward, in, and around the heart of the patient. The computing system might then generate one or more XR images, based at least in part on the generated one or more recommendations, and might present the generated one or more XR images using a UX device.
    Type: Application
    Filed: March 22, 2022
    Publication date: November 17, 2022
    Inventors: Peter N. Braido, Randal C. Schulhauser, Xiaohong Zhou, Alan Cheng, Zhongping Yang
  • Patent number: 11476328
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: October 18, 2022
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Patent number: 11024708
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yongliang Li, Xiaohong Cheng, Qingzhu Zhang, Huaxiang Yin, Wenwu Wang
  • Publication number: 20210151561
    Abstract: A stacked nanowire or nanosheet gate-all-around device, including: a silicon substrate; stacked nanowires or nanosheets located on the silicon substrate, extending along a first direction gate stacks and including multiple nanowires or nanosheets that are stacked; a gate stack, surrounding each of the stacked nanowires or nanosheets, and extending along a second direction, where first spacers are located on two sidewalls of the gate stack in the first direction; source-or-drain regions, located at two sides of the gate stack along the first direction; a channel region, including a portion of the stacked nanowires or nanosheets that is located between the first spacers. A notch structure recessed inward is located between the stacked nanowires or nanosheets and the silicon substrate, and includes an isolator that isolates the stacked nanowires or nanosheets from the silicon substrate. A method for manufacturing the stacked nanowire or nanosheet gate-all-around device is further provided.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG
  • Publication number: 20210151557
    Abstract: A semiconductor device, including: a silicon substrate; multiple fin structures, formed on the silicon substrate, where each extends along a first direction; a shallow trench insulator, located among the multiple fin structures; a gate stack, intersecting with the multiple fin structures and extending along a second direction, where first spacers are formed on two sidewalls in the first direction of the gate stack; source-or-drain regions, formed on the multiple fin structures, and located at two sides of the gate stack along the first direction; and a channel region, including a portion of the multiple fin structures located between the first spacers. and notch structures. A notch structure recessed inward is located between each of the multiple fin structures and the silicon substrate. The notch structure includes an isolator that isolates each of the multiple fin structures from the silicon substrate.
    Type: Application
    Filed: March 20, 2020
    Publication date: May 20, 2021
    Inventors: Yongliang LI, Xiaohong CHENG, Qingzhu ZHANG, Huaxiang YIN, Wenwu WANG